Pin Must-Connects for IC Cell Performance
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Solution Overview
Problem
Conventional integrated circuit fabrication processes face challenges in scaling to smaller technology nodes due to variability and constraints, limiting the number of vias per pin, which affects cell performance, especially at 10 nm or sub-10 nm ranges.
Innovation Solution
Implementing 'pin must-connects' where cells with multiple interconnect lines require more than two vias on a single net, maximizing via connections to match the number of interconnect lines, enhancing cell performance by optimizing via placement and routing at the block level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nm or sub-10 nm nodes
Solution Approach 1:
The patent segments the via connection requirement by pin type: pins with ≤2 interconnect lines use single via connections, while pins with >2 interconnect lines use multiple via connections. This segmentation allows the design to optimize for manufacturing precision where needed (multiple vias for high-density pins) while maintaining simplicity where applicable (single via for lower-density pins), resolving the contradiction between precision and complexity.
2Productivity
If the number of vias per pin is limited, then manufacturing simplicity is maintained, but cell performance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating via connection strategies based on local pin characteristics. Pins with more interconnect lines (higher local density) receive multiple via connections to maximize performance, while pins with fewer lines use single via connections. This localized optimization resolves the contradiction by tailoring via complexity to the specific performance needs of each pin rather than applying a uniform constraint.
3Productivity
If multiple vias are used per pin, then cell performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements partial action by applying multiple via connections only where necessary (pins with >2 interconnect lines) rather than universally. This partial application of the complex via strategy maximizes performance benefits for high-density pins while avoiding the increased manufacturing precision burden for all pins, thus resolving the contradiction between performance improvement and precision requirements.
Data Source
AI summary
An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.