PIN Photodiode P+ Layer Tapering to Prevent Wiring Collapse
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Solution Overview
Problem
PIN-type photodiodes with a P+ layer formed using amorphous silicon exhibit lower etching rates during dry etching, leading to pent roof-shaped edge structures, which can cause metal wiring to collapse due to the higher crystallinity of the P+ layer compared to the I layer.
Innovation Solution
Deteriorating the crystallinity of the P+ layer through boron ion implantation to match the etching rate with the I layer, ensuring the edges are formed in forward tapered shapes and preventing metal wiring collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the P+ layer is formed with high crystallinity to ensure electrical conductivity, then the electrical conductivity is improved, but the etching rate becomes lower than that of the I layer, causing pent roof-shaped structures to form at the edges
Solution Approach 1:
The patent applies local quality by differentiating the treatment of the P+ layer: the central region maintains high crystallinity for electrical conductivity, while the edge regions undergo crystallinity reduction to match the etching rate with the I layer. This is achieved through selective ion implantation or controlled etching processes that affect only specific regions of the P+ layer, allowing simultaneous optimization of both conductivity and edge shape uniformity.
Solution Approach 2:
The patent changes the crystallinity parameter of the P+ layer in specific regions to resolve the contradiction. By reducing crystallinity at the edges through ion implantation (e.g., with fluorine or chlorine ions) or thermal treatment, the etching rate of the P+ layer edge is increased to match that of the I layer, preventing pent roof formation while the central region retains high crystallinity for conductivity.
2Manufacturing precision
If the etching rate of the P+ layer is increased to match the I layer, then the edge shape uniformity is improved, but the crystallinity deteriorates, potentially affecting electrical conductivity
Solution Approach 1:
The patent applies local quality by differentiating the treatment of the P+ layer: the central region maintains high crystallinity for electrical conductivity, while the edge regions undergo crystallinity reduction to match the etching rate with the I layer. This is achieved through selective ion implantation or controlled etching processes that affect only specific regions of the P+ layer, allowing simultaneous optimization of both conductivity and edge shape uniformity.
Solution Approach 2:
The patent applies preliminary action by pre-treating the P+ layer edges with ion implantation or thermal processing before the main etching step. This preliminary crystallinity reduction at the edges ensures that during subsequent etching, the P+ layer and I layer etch at matching rates, producing uniform forward tapered edges without compromising the bulk conductivity of the P+ layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the electrical conductivity of the P+ layer is maintained while preventing pent roof structures, resulting in a highly reliable semiconductor device with improved manufacturing consistency.
Implementation Method 1
executing boron ion implantation on the P+ layer after the formation of the P+ layer
Data Source
AI summary
The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.