Pin Up Interconnects in IC Packages
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Solution Overview
Problem
Current interconnecting substrates for semiconductor packaging face issues such as heat treatment-induced defects, faulty connections, and stress-related opening defects, which affect the reliability of the connections and integration density.
Innovation Solution
A method for fabricating an integrated circuit package involving multiple layers of conductive plating and photo-resist materials to form interconnects, including stud conductive plating, epoxy or polymide compounds, and semi-additive processing for precise etching and surface leveling, ensuring reliable connections and stress reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If glass epoxy print substrate is used as base core substrate for build-up multi-layered substrate fabrication, then interconnection density can be achieved, but heat treatments cause poor substrate condition and defects
Solution Approach 1:
The patent extracts the problematic glass epoxy print substrate from the build-up multi-layered substrate structure and replaces it with a ceramic substrate. This removal eliminates the source of heat treatment-induced defects while preserving the interconnection density capability through alternative materials and processes.
Solution Approach 2:
The patent changes the fundamental material parameter of the substrate from organic glass epoxy to inorganic ceramic material. This parameter change fundamentally alters the thermal and mechanical properties, enabling the substrate to withstand heat treatments without degradation while maintaining manufacturing precision for high-density interconnections.
2Ease of manufacture
If heat treatments are performed during chip loading and solder reflow, then assembly can be completed, but faulty connections and distortion occur affecting long-term reliability
Solution Approach 1:
The patent applies beforehand cushioning by pre-establishing a stress-compensating structure in the substrate design. The ceramic substrate and its integrated compensation layer are designed to anticipate and counteract the thermal stresses that will occur during chip loading and solder reflow, preventing distortion and connection failures before they happen.
3Adaptability or versatility
If mounting is performed on external board or apparatus, then device can be integrated, but stress concentrates on interface between external electrode terminal and insulating layer causing opening defects
Solution Approach 1:
The patent employs composite materials by integrating a stress compensation layer within the ceramic substrate structure. This composite design combines materials with complementary properties to distribute mounting stress away from the vulnerable interface between external electrode terminals and insulating layers, preventing opening defects while maintaining integration capability.
4Manufacturing precision
If build-up multi-layered substrate structure is fabricated, then interconnection layers and via conductors are formed, but multiple heat treatments cause cumulative damage and defects
Solution Approach 1:
The patent extracts the problematic sequential heat treatment process from the fabrication methodology and replaces it with a ceramic substrate-based approach. The ceramic material inherently withstands the necessary thermal processes without degradation, allowing precise formation of interconnection structures and via conductors without cumulative heat-induced damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability and long-term stability of interconnects by reducing defects and improving mounting reliability, allowing for higher integration density and performance in semiconductor devices.
Implementation Method 1
plating method and the photolithography with a combination of the electroless or electrolytic Cu, in which an interconnection layer and via conductors are formed
Implementation Method 2
plating method and the photolithography with a combination of the electroless or electrolytic Cu, in which an interconnection layer and via conductors are formed
Data Source
AI summary
An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.