Asynchronous Ping-Pong Counter for High-Speed Edge Counting
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Solution Overview
Problem
Existing synchronous counters fail to meet setup and hold timing requirements when the fast clock operates at high speeds, such as 5 GHz, and the slow clock at extremely low speeds, like 10 MHz, making it impossible to accurately count rising edges.
Innovation Solution
An asynchronous ping-pong counter is designed, comprising an edge detector, a dual asynchronous counter, and a finite state machine, which uses a pulse signal to manage rising edges across time slots and selects which asynchronous counter outputs the count value based on a binary select signal, allowing efficient counting of rising edges between neighboring slow clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a synchronous counter is used to count rising edges of a fast clock (5 GHz) based on a slow clock (10 MHz), then the counting function can be implemented, but the setup and hold timing requirements of flip-flops cannot be met
Solution Approach 1:
The counter is divided into two separate asynchronous counters (first and second asynchronous counters) that operate independently. Each counter handles a portion of the counting function, allowing them to process high-frequency clock edges without the timing constraints that would affect a single synchronous counter. This segmentation enables accurate counting at 5 GHz while avoiding flip-flop timing violations.
Solution Approach 2:
The system uses periodic switching between the first and second asynchronous counters based on the slow clock signal. When the slow clock transitions, the system alternates which counter is actively counting, allowing each counter to complete its counting function within valid timing windows. This periodic action enables the system to meet timing requirements while maintaining accurate counts of high-frequency edges.
2Productivity
If the fast clock operates at very high speed (5 GHz) and the slow clock at extremely low speed (10 MHz), then the counting range is sufficient, but synchronous counters cannot meet timing requirements
Solution Approach 1:
The system dynamically switches between the first and second asynchronous counters based on the state of the slow clock. This dynamic operation allows the counters to adapt to the large frequency difference between the fast clock (5 GHz) and slow clock (10 MHz), enabling high-speed counting while maintaining reliability by ensuring each counter operates within valid timing windows through coordinated switching.
3Measurement precision
If a synchronous counter is used to oversample the slow clock, then the counting function can be implemented, but it is almost impossible to meet both setup and hold timing requirements
Solution Approach 1:
The invention extracts the timing-critical counting function from the synchronous domain and places it in the asynchronous domain. By using asynchronous counters that directly respond to clock edges without requiring synchronized operation, the system eliminates the complex setup and hold timing constraints that would otherwise be required for accurate rising edge detection at high frequencies.
Data Source
AI summary
An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.