Pinless IC Testing via Central Test Engine
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Solution Overview
Problem
The increasing processing speed and data transfer rate of integrated circuits (ICs) lead to higher test costs and times during the production phase, as existing testing methods require extensive external hardware and multiple interface pins, complicating high-volume manufacturing and limiting efficiency.
Innovation Solution
The integration of a Central Test Engine (CTE) within the IC as a hardware abstraction layer, which generates test patterns autonomously and reduces the need for external testing hardware, using interface pins like GPIO or JTAG, thereby eliminating the need for external test access mechanisms and interface controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional external testing hardware and multiple interface pins are used for IC testing, then testing coverage and reliability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the testing functionality into the IC itself by integrating a built-in self-test (BIST) mechanism. The IC contains internal test generators, pattern generators, and response analyzers that combine multiple testing functions into a single integrated system, eliminating the need for separate external testing hardware and reducing overall system complexity while maintaining testing reliability.
Solution Approach 2:
The IC performs self-testing through built-in self-test (BIST) capabilities where the device tests itself without external assistance. The internal test logic generates test patterns, applies them to the circuit under test, and analyzes responses autonomously, allowing the IC to service its own testing needs and reducing dependence on complex external testing equipment.
2Productivity
If the number of IO pins is increased to support high-volume manufacturing testing, then testing capability is improved, but manufacturing cost and production time increase
Solution Approach 1:
The built-in test engine serves multiple functions: it generates test patterns, stimulates circuit elements, captures responses, and analyzes test results. This multi-functional integration allows a single test interface to perform what previously required multiple dedicated IO pins, reducing the quantity of pins needed while maintaining high-volume manufacturing testing capability.
Solution Approach 2:
The patent extracts the testing functionality from the external hardware domain and relocates it into the IC's internal logic. By taking out the test pattern generation and response analysis functions from external equipment and embedding them within the IC, the design reduces the number of external interface pins required while preserving comprehensive testing capabilities.
3Speed
If processing speed and data transfer rate of ICs are increased, then performance is improved, but testing time and cost increase
Solution Approach 1:
The built-in self-test mechanism enables continuous testing operations that can run concurrently with normal IC operation or immediately upon power-up. The internal test engine continuously generates test patterns and analyzes responses without interruption, eliminating idle testing time and allowing testing to proceed continuously alongside other manufacturing processes, thereby reducing overall testing time despite high processing speeds.
Data Source
AI summary
A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.