Pinned Bit Line Structure for Higher-Density DRAM Fabrication
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Solution Overview
Problem
As semiconductor devices, such as DRAM, continue to shrink, it becomes increasingly difficult to fabricate interconnecting structures for memory cells, and existing designs struggle to achieve higher device density and performance while maintaining efficient fabrication processes.
Innovation Solution
The implementation of a comb-shaped or fence-shaped bit line structure with pins optionally connected to transistors, fabricated using a dual damascene process, which allows for improved functionality and performance by simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional interconnecting structures are used in shrinking DRAM devices, then device density can be maintained, but fabrication difficulty increases significantly
Solution Approach 1:
The bit line is divided into multiple segments including pin portions extending into the substrate and horizontal portions at different heights. This segmentation allows each part to serve specific functions while simplifying the overall fabrication process by enabling modular formation through dual damascene techniques
Solution Approach 2:
The bit line structure transitions from a conventional planar configuration to a three-dimensional structure with pins extending vertically into the substrate and horizontal portions at different elevations. This dimensional change enables improved signal transmission while maintaining compatibility with standard fabrication processes
2Productivity
If various cell designs are implemented to achieve higher device density, then product needs are fulfilled, but fabrication complexity increases
Solution Approach 1:
The comb-shaped or fence-shaped bit line structure serves multiple functions: it provides electrical connection to memory cells, enables signal transmission, and can be configured with pins either connected or not connected to transistors. This multi-functionality allows a single structure to fulfill various design requirements without necessitating different fabrication processes
Solution Approach 2:
The bit line structure allows for parameter variations such as pin length, pin spacing, and connection configuration to substrate or transistor. These parameter changes enable adaptation to different cell designs and density requirements while maintaining the same fundamental fabrication approach
3Ease of manufacture
If conventional bit line structures are used, then fabrication process is simpler, but device performance is limited
Solution Approach 1:
By extending bit line pins vertically into the substrate and creating horizontal portions at different heights, the structure improves signal transmission characteristics and electrical connection reliability while still being fabricated through standard dual damascene processes used in conventional manufacturing
Data Source
AI summary
The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.