PIP Gate Structure for Stable Split-Gate Spacing in High-Voltage Devices
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Solution Overview
Problem
Conventional high voltage devices face challenges in minimizing size due to thick RESURF oxide layers, leading to prolonged gate-split gate distances and deformation of split gates, complicating manufacturing processes.
Innovation Solution
A polysilicon-insulator-polysilicon (PIP) structure is introduced, where polysilicon regions and insulation regions are formed through self-aligned processes, allowing precise control of gate-split gate distance and preventing deformation by stacking effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the RESURF oxide layer is increased, then the high voltage device can withstand higher voltages, but the distance between the gate and the split gate is prolonged
Solution Approach 1:
The patent transitions from a conventional planar structure to a three-dimensional PIP structure where the gate and split gate are stacked vertically with an insulation layer between them. This vertical arrangement allows the gate-split gate distance to be determined by the insulation layer thickness rather than the RESURF oxide layer thickness, resolving the contradiction between voltage withstanding capability and gate distance.
Solution Approach 2:
The patent embeds the insulation layer within the PIP structure between the gate and split gate, creating a nested configuration. This nested structure allows the insulation layer to provide both electrical isolation and mechanical support, enabling independent control of the gate-split gate distance without affecting the voltage withstanding capability provided by the RESURF oxide layer.
2Area of stationary object
If the distance between the gate and the split gate is shortened to reduce device size, then the device area is reduced, but the split gate drifts and deforms due to stack effects
Solution Approach 1:
The patent introduces an insulation layer as an intermediary between the gate and split gate in the PIP structure. This insulation layer acts as a mediator that provides mechanical support and prevents direct contact between the two gates, eliminating the stack effects that cause drift and deformation while allowing short gate distance for compact device area.
Solution Approach 2:
The PIP structure employs a composite configuration combining polysilicon regions with an insulation layer. This composite structure distributes mechanical stresses and prevents deformation of the split gate while maintaining compact dimensions, as the insulation layer provides structural support that compensates for the reduced distance between gates.
3Reliability
If multiple layers (spacer layer, self-aligned oxide layer, RESURF oxide layer) are stacked between the gate and split gate, then voltage withstanding capability is improved, but manufacturing process control becomes very difficult
Solution Approach 1:
The patent extracts the insulation layer function from the complex multi-layer stack and implements it as a dedicated insulation layer within the PIP structure. This separation of functions simplifies the manufacturing process by eliminating the need to precisely control multiple stacked layers, as the insulation layer can be formed independently with standard semiconductor fabrication techniques.
Solution Approach 2:
The patent changes the structural parameters by adopting the PIP configuration with a clearly defined insulation layer thickness that directly determines the gate-split gate distance. This parameter change simplifies process control compared to the conventional approach where multiple layer thicknesses must be precisely controlled, as only the insulation layer thickness needs to be precisely managed.
Data Source
AI summary
A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.