Picture-in-Picture Timing Control for Smooth Zoomed Video

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Solution Overview

Problem

Existing graphics systems struggle to instantly generate a zoomed-in picture-in-picture (PIP) window without causing visual stuttering or discontinuities, especially when changing the position of the target region or zoom-in scale.

Innovation Solution

A graphics system comprising a frame buffer, processing unit, and timing controller that controls the input and output timings to ensure the PIP window is generated smoothly by adjusting vertical synchronization signals and frequencies, using phase differences and Quick Frame Transport (QFT) parameters to optimize the display process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processing unit reads and writes video frames in real-time to generate PIP window, then the PIP window can be displayed instantly, but visual stuttering or discontinuities occur when changing target region or zoom-in scale

Engineering Contradiction:
Improvereal-time generation speedVSAvoidvisual continuity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The timing controller pre-calculates and pre-positions the second reading point before the second writing point to ensure that the target region data is ready in advance. This preliminary action prevents visual stuttering by ensuring data availability before it is needed for PIP window generation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The timing controller continuously monitors and adjusts the phase difference between input and output timing signals. By using feedback control, the system dynamically maintains the correct temporal relationship between frame writing and reading operations, preventing visual discontinuities during real-time PIP window generation.

Inventive Principle:
Principle #23Feedback

2Reliability

If the timing controller adjusts vertical synchronization signals to maintain phase difference, then visual continuity is maintained, but system complexity increases

Engineering Contradiction:
Improvevisual continuityVSAvoidtiming control mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The timing controller serves as an intermediary component that mediates between the processing unit's frame writing operations and the display's frame reading operations. By introducing this dedicated timing control intermediary, the system maintains visual continuity through centralized phase difference management without requiring complex modifications to the processing unit or display device.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the second reading point precedes the second writing point, then data availability is ensured, but additional timing buffer requirements increase memory usage

Engineering Contradiction:
Improvedata availabilityVSAvoidmemory buffer size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system changes the timing parameters by adjusting the phase difference between vertical synchronization signals. By modifying when the second reading point occurs relative to the second writing point, the system ensures data availability while minimizing the required buffer size to only what is necessary for the phase offset, rather than requiring large buffers for entire frames.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12555178B2Graphics system
Publication Date: 2026.02.17 MEDIATEK INC
  • US12555178B2 patent drawing
  • US12555178B2 patent drawing
  • US12555178B2 patent drawing

AI summary

A graphics system is provided. The graphics system includes a frame buffer, a timing controller, and a processing unit. The processing unit generating an output video frame based on a raw video frame. The output video frame includes the main window and a picture-in-picture window overlaid on the main window, and the picture-in-picture window is generated by zooming in a target region of the main window. The timing controller is configured to generates a first vertical synchronization signals to control the input timing for the processing unit to write the raw video frame into the frame buffer, and generate a second vertical synchronization signal to control an output timing for the processing unit to read the raw video frame from the frame buffer and generating the output video frame, such that specific timing conditions are met.