3D Non-Volatile Memory Pipe Gate Structure for Erase Control
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Solution Overview
Problem
Conventional 3-D non-volatile memory devices face challenges in controlling the etching of insulating layers, impurity diffusion, and erase operation efficiency due to irregularities in conductive plug formation, leading to variations in erase speed and transistor characteristics.
Innovation Solution
The proposed solution involves forming a 3-D non-volatile memory device with a pipe gate structure, including a first and second pipe gate, and a method of manufacturing that involves specific etching and layer formation to enhance the electric field and control the overlap of gates and junctions, allowing for improved erase operations by forming conductive plugs with precise doping and recessing insulating layers for consistent channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive plugs are formed by depositing polysilicon and implanting ions or depositing polysilicon doped with high concentration impurities, then the erase operation can be performed in depletion mode, but it is difficult to control the etching of the insulating layer and the diffusion of impurities, leading to irregular conductive plug formation and variations in transistor characteristics
Solution Approach 1:
The patent applies preliminary action by forming the insulating layer with a pre-defined recessed region before forming the conductive plug. This recessed region is created in advance to control the final shape and position of the conductive plug, ensuring consistent overlap with the source gate. The insulating layer is recessed to a specific depth using etching processes that are performed before conductive plug formation, allowing precise control over the junction geometry and eliminating variations in transistor characteristics.
2Productivity
If the source gate excessively overlaps with the junction to generate sufficient holes for erase operation, then the erase operation efficiency is improved, but leakage occurs in the source select transistor
Solution Approach 1:
The patent applies local quality by creating a recessed region in the insulating layer at a specific location where the conductive plug will be formed. This local modification allows the conductive plug to have a controlled overlap with the source gate - sufficient to generate holes for erase operation but limited to prevent excessive overlap that would cause leakage. The recessed region is formed only in the necessary area, maintaining proper electrical characteristics while enabling effective erase operation.
3Manufacturing precision
If the insulating layer is etched to form the recessed region for conductive plug formation, then the overlap between gate and junction can be controlled, but the etching process becomes complex and difficult to control
Solution Approach 1:
The patent uses the insulating layer as an intermediary element to control the overlap between the gate and junction. By forming a recessed region in this insulating layer, the patent creates a template that guides the subsequent formation of the conductive plug. This intermediary structure simplifies the overall process by providing a pre-defined geometry that automatically ensures proper overlap control, eliminating the need for complex multi-step etching processes or precise alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the efficiency of erase, read, and program operations, reduces variations in erase speed, and enhances the swing characteristics of select transistors, resulting in improved performance and reliability of the 3-D non-volatile memory device.
Implementation Method 1
The conductive plugs 21 are formed by depositing a polysilicon layer and subsequently implanting the ions of impurities or depositing polysilicon doped with impurities of a high concentration.
Implementation Method 2
The conductive plugs 21 are formed by depositing a polysilicon layer and subsequently implanting the ions of impurities
Implementation Method 3
The erase operation of the 3-D non-volatile memory device constructed as above is performed in a depletion mode in which holes generated due to Gate Induced Drain Leakage (GIDL) in the junction are used in the erase operation. That is, the erase operation is performed in such a manner that the holes generated by GIDL are moved along the channel layer 19 and subsequently injected into the charge trap layers of the memory cells.
Data Source
AI summary
A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.