Pipe Latch Parallel Inverter Stages

Solution Overview

Problem

Existing memory devices face challenges in reducing errors during continuous data input/output operations, and they also consume excessive power and have a large size due to the number of transistors in pipe latches.

Innovation Solution

The implementation of a pipeline system with a pipe latch configuration that includes a first inverter latch and multiple second inverter latches in parallel, controlled by switches activated by clock signals, to efficiently store and transfer data entries while minimizing transistor count and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple pipe latches are used to temporarily store and transfer continuously input/output data entries, then data transfer reliability is improved, but power consumption increases and device size increases due to the number of transistors

Engineering Contradiction:

Improvedata transfer reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pipe latch is divided into multiple stages (first stage, second stage, third stage) with each stage handling specific data transfer functions. This segmentation allows data to be processed in discrete steps through separate latch groups, improving reliability through staged verification while enabling power management by selectively activating only necessary stages during operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pipe latch operates using periodic clock signals (first clock signal, second clock signal, third clock signal) that control the timing of data transfer between stages. This periodic operation allows the circuit to enter low-power states between active transfer cycles, reducing average power consumption while maintaining reliable data transfer through synchronized staged operations.

Inventive Principle:

Principle #19Periodic action

2Reliability

If multiple pipe latches are used to temporarily store and transfer continuously input/output data entries, then data transfer reliability is improved, but device size increases due to the number of transistors

Engineering Contradiction:

Improvedata transfer reliabilityVSAvoiddevice size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The pipe latch is divided into multiple stages (first stage, second stage, third stage) with each stage handling specific data transfer functions. This segmentation allows data to be processed in discrete steps through separate latch groups, improving reliability through staged verification while enabling power management by selectively activating only necessary stages during operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pipe latch circuit is designed to handle multiple data transfer functions using the same basic latch structure repeated across stages. The first latch group, second latch group, and third latch group all perform similar data storage and transfer functions, allowing the circuit to maintain reliability through functional redundancy without proportionally increasing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If a traditional pipe latch configuration is used, then data entries can be stored and transferred, but error rate increases during continuous data input/output operations

Engineering Contradiction:

Improvedata input/output throughputVSAvoiddata transfer accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The pipe latch is divided into multiple stages (first stage, second stage, third stage) with each stage handling specific data transfer functions. This segmentation allows data to be processed in discrete steps through separate latch groups, improving reliability through staged verification while enabling power management by selectively activating only necessary stages during operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The multi-stage pipe latch configuration provides implicit feedback mechanisms where each stage verifies data before passing it to the next stage. The first latch group, second latch group, and third latch group operate in sequence, allowing error detection and correction opportunities at each transition point, thereby maintaining high data transfer accuracy during continuous operations.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250124957A1Memory device including pipe latch

Publication Date: 2025.04.17 SK HYNIX INC

AI summary

A pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. Plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. Plural second switches are configured to output the plural data entries stored in the plural second inverter latches.