Pipe Latch Output Switching for Probe-Testable Bump Pad ICs

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Solution Overview

Problem

The chip-on-chip package technology for semiconductor ICs limits probe test capabilities due to small bump pad sizes, requiring separate larger probe test pads, which increases chip area and production costs.

Innovation Solution

A semiconductor IC with a chip-on-chip structure that includes first and second bump pads, a probe test pad, and a pipe latch unit that selectively transfers data to either the bump pads or the probe test pad based on operating mode, optimizing pad arrangement for efficient testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If chip-on-chip package technology is used to increase operating frequency and reduce chip area, then operating speed is improved and overall chip area is reduced, but bump pad size becomes too small to perform proper probe testing

Engineering Contradiction:

Improveoperating frequencyVSAvoidprobe test capability

Core Design Contradiction:

SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The invention segments the testing function from the data output function by providing separate probe test pads distinct from the bump pads. The probe test pads are specifically designed for testing purposes while bump pads are optimized for data transmission, allowing each to fulfill its function without compromise.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention introduces probe test pads as intermediary elements that facilitate testing without interfering with the bump pads. These test pads act as mediators between the internal circuitry and external testing equipment, enabling probe testing while maintaining the integrity and size optimization of the bump pads.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If separate probe test pads are provided to enable proper probe testing, then probe test capability is improved, but chip area increases and production costs increase

Engineering Contradiction:

Improveprobe test capabilityVSAvoidchip area

Core Design Contradiction:

Difficulty of detecting and measuringVSArea of stationary object

Solution Approach 1:

The invention applies local quality by making different parts of the chip serve different functions with different characteristics. Probe test pads are located at specific positions optimized for testing access, while bump pads are positioned for data transmission. Each pad type has its size and location optimized for its specific purpose, allowing efficient use of chip area.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The invention utilizes spatial arrangement in multiple dimensions to accommodate both probe test pads and bump pads efficiently. By strategically positioning test pads at locations that do not conflict with bump pad requirements and by arranging them in optimized patterns, the design achieves both testing capability and area efficiency.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20110156748A1Semiconductor integrated circuit

Publication Date: 2011.06.30 SK HYNIX INC

AI summary

A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.