Pipe Latch Device for Semiconductor Memory Output Timing Control
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Solution Overview
Problem
Semiconductor memory devices, such as DDR II SDRAM, face challenges in reducing unnecessary current consumption and size due to inefficiencies in data processing and output timing.
Innovation Solution
The implementation of a semiconductor memory device with an output controller and input controller that utilize delay locked loop (DLL) clock signals and driving signals to synchronize data output through a pipe latch unit, incorporating shifters and output control signal drivers to manage data latching and output in synchronization with DLL clock signals, thereby reducing power consumption and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is latched and output sequentially through pipe latch units, then data collision is prevented and output timing is controlled, but unnecessary current consumption increases due to continuous operation of output control circuits
Solution Approach 1:
The patent implements periodic activation of output control signal drivers based on DLL clock phases. The output controller alternates between first and second output control signal groups in synchronization with rising and falling edges of the DLL clock, activating only the necessary drivers at each phase rather than maintaining continuous operation. This periodic action reduces current consumption while maintaining reliable data output timing control.
2Reliability
If multiple output control signal groups are generated for rising and falling DLL clock edges, then data output synchronization is improved, but device size increases due to additional control circuits
Solution Approach 1:
The patent merges the functionality of multiple output control signal drivers into a unified output controller structure. The first and second output control signal groups are generated by the same output controller based on phase information from the DLL clock, sharing common control logic and signal distribution pathways. This merging approach maintains output synchronization for both rising and falling edges while reducing overall device size compared to having completely separate control circuits.
Solution Approach 2:
The output controller is designed with multi-functionality to generate both first and second output control signal groups using the same hardware structure. The controller responds to both rising and falling edges of the DLL clock and produces corresponding output control signals through a universal control mechanism, eliminating the need for duplicate specialized circuits and thereby reducing device complexity.
3Manufacturing precision
If shifters delay input data signals by half clock and one clock, then data output timing is precisely controlled, but manufacturing complexity increases
Solution Approach 1:
The patent segments the data delay function into distinct shifter units that provide fixed delay stages (half clock and one clock). Each shifter is designed as a modular component with standardized delay characteristics, allowing precise timing control through组合 of these segmented delay elements. This segmentation approach simplifies manufacturing by using repeated standardized units rather than custom-designed complex delay circuits.
Data Source
AI summary
A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.