Pipe Transistor Voltage Adjustment for Memory Programming

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Solution Overview

Problem

Semiconductor memory devices face program disturbance issues during programming operations due to variations in channel boosting levels, which can lead to inefficiencies and data integrity problems.

Innovation Solution

A semiconductor memory device with a control logic system that adjusts the potential level of the pipe transistor operation voltage based on the address of a selected page, allowing for precise control of program operations and minimizing channel boosting level variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed pipe transistor operation voltage is applied during program operation, then the programming operation can be performed, but program disturbance occurs due to channel boosting level variations

Engineering Contradiction:

Improvedata integrityVSAvoidprogram disturbance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the pipe transistor operation voltage adjustable rather than fixed. The control logic dynamically changes the potential level of the pipe transistor operation voltage based on the address of the selected page, allowing the system to adapt to different programming scenarios and prevent program disturbance caused by channel boosting level variations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of pipe transistor operation voltage based on the selected page address. By adjusting the potential level of the pipe transistor operation voltage according to different pages being programmed, the system optimizes the programming operation and prevents program disturbance in other memory cells.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the pipe transistor operation voltage is adjusted according to page address, then program disturbance is prevented, but the control complexity increases

Engineering Contradiction:

Improveprogram operation stabilityVSAvoidcontrol logic complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by making different pages have different pipe transistor operation voltages based on their addresses. Each page receives a tailored voltage level appropriate for its specific programming needs, which prevents program disturbance in other memory cells while maintaining overall system reliability.

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If uniform programming voltage is applied to all memory cells, then the programming process is simple, but channel boosting level variations cause program disturbance

Engineering Contradiction:

Improveprogramming process simplicityVSAvoidchannel boosting level variations

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent changes the pipe transistor operation voltage parameter based on the selected page address to compensate for channel boosting level variations. This approach maintains programming process simplicity while effectively preventing program disturbance caused by voltage variations across different memory cells.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10020057B2Semiconductor memory device and operating method thereof with a connection control transistor operation voltage adjusted

Publication Date: 2018.07.10 SK HYNIX INC

AI summary

There is provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation by applying a program voltage, a pass voltage, and a pipe transistor operation voltage, to the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform the program operation, wherein the control logic adjusts a potential level of the pipe transistor operation voltage according to an address of a selected page among the plurality of pages.