Pipeline ADC Capacitor Averaging With 2-Phase Switched-Capacitor Stages
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Solution Overview
Problem
Existing capacitor averaging converters in pipeline analog-to-digital converters face limitations due to high power consumption and slow data conversion rates, primarily because they require multiple clock phases and idle opamps, which restrict their operating speed and efficiency.
Innovation Solution
The implementation of a 2-phase clock scheme using two parallel switched capacitor circuits per stage, where each stage has both a first and a second switched capacitor circuit for simultaneous residual signal amplification and averaging, with operational amplifiers continuously active to reduce power consumption and increase throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated opamp-based switched-capacitor stage is used to perform charge averaging in a separate averaging phase, then capacitor mismatch compensation is achieved, but power consumption increases and operating speed is limited to 20 Msps
Solution Approach 1:
The patent combines the residual signal amplification function and the charge averaging function into a single switched-capacitor circuit. The same circuit that amplifies the residual signal also performs the averaging operation by redistributing charges among capacitors during the same clock phases, eliminating the need for a separate dedicated averaging stage and its associated power consumption.
Solution Approach 2:
The switched-capacitor circuit is designed to perform multiple functions: it acts as both the residual amplifier and the averaging mechanism. By making the circuit universal, the patent eliminates redundant components and reduces overall power consumption while maintaining the required compensation functionality.
2Measurement precision
If four clock phases are required to output one residual signal from each pipeline stage, then proper averaging operation is achieved, but data conversion rate is significantly slower
Solution Approach 1:
The patent implements a periodic charge redistribution scheme where charges are sampled and averaged in alternating clock phases. During Φ3, charges are sampled into first capacitors, and during Φ4, they are redistributed to second capacitors with different gains. This periodic action maintains averaging accuracy while reducing the total number of clock phases required.
Solution Approach 2:
The patent ensures continuous useful action by having pipeline stages operate in an overlapped manner. While one stage is performing amplification in Φ3, the next stage can be sampling in Φ1 or Φ2, eliminating idle periods and maximizing the throughput of the converter without compromising the averaging operation.
3Use of energy by moving object
If switches are added to control double sampling of residual signals, then passive capacitor averaging reduces power dissipation, but device complexity increases
Solution Approach 1:
The patent segments the switched-capacitor circuit into distinct phases with clearly defined switch configurations. By dividing the operation into sampling phase (Φ1, Φ2) and amplification/averaging phase (Φ3, Φ4), the control logic for each switch becomes simpler and more systematic, reducing overall control complexity despite the additional switches required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher data conversion rates and reduced power consumption by eliminating idle opamps and operating all stages in a 2-phase clock scheme, achieving high-resolution capacitor averaging at high speeds while minimizing power usage.
Implementation Method 1
twice samples the residual signal into two nominally identical capacitors of the next pipeline stages. The charges on the two capacitors are redistributed in an averaging manner among the shorted capacitors in the next clock phase
Data Source
AI summary
A capacitor-averaging pipeline analog-to-digital converter has a plurality of stages. Each of the plurality of stages has a first switched capacitor circuit and a second switched capacitor circuit parallel with the first switched capacitor circuit. A corresponding method is also disclosed.