Pipeline ADC Capacitor Sharing for Lower Power and Die Area
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Solution Overview
Problem
Conventional pipeline ADCs face limitations in reducing power consumption and die size due to the requirement of large capacitors for each stage to minimize capacitor mismatch and noise, leading to increased power consumption and larger die size.
Innovation Solution
The pipeline ADC employs capacitor sharing between adjacent stages through a periodic unit structure with inter-switchable capacitor networks, allowing for reduced total capacitor area and power consumption by eliminating the need for additional sampling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each stage uses large capacitors to minimize capacitor mismatch and KT/C noise, then measurement precision is improved, but area of stationary object increases and use of energy increases
Solution Approach 1:
The patent merges the sampling capacitor function into the existing hold capacitor structure. The hold capacitor serves dual purposes: holding the sampled voltage and performing the capacitive division operation. This eliminates the need for separate sampling capacitors in each stage, reducing total capacitor area while maintaining measurement precision through the operational amplifier's virtual ground technique
Solution Approach 2:
The hold capacitor is given multiple functions: it acts as both the sampling capacitor and the capacitive divider element in the feedback path. This multi-functionality reduces the total number of capacitors needed per stage from two (sampling + hold) to one (hold capacitor doing both jobs), directly addressing the area reduction goal while preserving accuracy
2Measurement precision
If each stage uses large capacitors to minimize capacitor mismatch and KT/C noise, then measurement precision is improved, but use of energy increases
Solution Approach 1:
By merging the sampling and hold capacitor functions into a single hold capacitor structure, the total capacitance per stage is reduced. Smaller capacitors require less charge storage and transfer, directly reducing dynamic power consumption in the capacitive DAC and operational amplifier circuits
Solution Approach 2:
The patent changes the operational parameters by using the operational amplifier's high gain to create a virtual ground, which allows the hold capacitor to perform capacitive division without requiring large capacitance values. This parameter change (using voltage feedback control) enables precision maintenance with smaller capacitor sizes, reducing power consumption
3Measurement precision
If sampling capacitors are added to each stage, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the sampling capacitor and hold capacitor into a single capacitor structure. The hold capacitor is connected to the inverting input of the operational amplifier, and during the sampling phase, it simultaneously performs sampling and voltage holding functions, eliminating the need for separate sampling capacitor circuits and reducing structural complexity
Solution Approach 2:
The hold capacitor is designed to perform multiple functions: sampling the input voltage, holding the sampled value during conversion, and providing capacitive division feedback. This multi-functional design eliminates the need for dedicated sampling capacitors and their associated switching circuits, reducing device complexity while maintaining sampling accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the total capacitor area and power consumption while maintaining accurate voltage output, contributing to a smaller die size without compromising performance.
Implementation Method 1
the virtual ground of the operational amplifier is adapted to be coupled to a first terminal of the reference capacitor
Implementation Method 2
a first capacitor network and a second capacitor network for each periodic unit, the first and second capacitor networks both coupled to a corresponding periodic unit and having an identical structure
Data Source
AI summary
A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.