Pipeline ADC Dither Injection via Shifted Quantization References

Solution Overview

Problem

Conventional pipeline analog-to-digital converters with input dithers face challenges in power consumption, area, and design difficulty due to the requirement of a high-performance sample-and-hold circuit, which consumes a significant portion of the power and area of the entire converter.

Innovation Solution

A pipeline analog-to-digital converter architecture with dither pre-quantization technology that injects dithers directly into the input signal within the multiplying digital-to-analog conversion module, eliminating the need for a sample-and-hold circuit and using a novel quantization reference level generating circuit to shift comparator levels, thereby achieving equivalent dither injection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a sample-and-hold circuit is used to inject dithers in conventional pipeline ADCs, then dither injection function is achieved, but power consumption and area increase significantly

Engineering Contradiction:

Improvedither injection functionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the dither injection function from the traditional sample-and-hold circuit and relocates it to the quantization reference level generating circuit. By removing the dedicated sample-and-hold circuit while preserving its dither injection capability through the modified reference level circuit, power consumption and area are significantly reduced while maintaining the essential dither injection function for improving ADC linearity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The quantization reference level generating circuit is designed to serve multiple functions: it generates the quantization reference levels for the flash ADC comparators and simultaneously injects the dither signal by randomly selecting reference levels. This multi-functionality eliminates the need for separate sample-and-hold circuitry, reducing overall power consumption and circuit area while maintaining both ADC operation and dither injection.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a sample-and-hold circuit is used to inject dithers in conventional pipeline ADCs, then dither injection function is achieved, but device complexity and design difficulty increase

Engineering Contradiction:

Improvedither injection functionVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the dither injection function from the traditional sample-and-hold circuit and relocates it to the quantization reference level generating circuit. By removing the dedicated sample-and-hold circuit while preserving its dither injection capability through the modified reference level circuit, power consumption and area are significantly reduced while maintaining the essential dither injection function for improving ADC linearity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The quantization reference level generating circuit is designed to serve multiple functions: it generates the quantization reference levels for the flash ADC comparators and simultaneously injects the dither signal by randomly selecting reference levels. This multi-functionality eliminates the need for separate sample-and-hold circuitry, reducing overall power consumption and circuit area while maintaining both ADC operation and dither injection.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If a sample-and-hold circuit is used to inject dithers in conventional pipeline ADCs, then dither injection function is achieved, but area occupied by the converter increases

Engineering Contradiction:

Improvedither injection functionVSAvoidconverter area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the dither injection function from the traditional sample-and-hold circuit and relocates it to the quantization reference level generating circuit. By removing the dedicated sample-and-hold circuit while preserving its dither injection capability through the modified reference level circuit, power consumption and area are significantly reduced while maintaining the essential dither injection function for improving ADC linearity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the dither injection function with the quantization reference level generating circuit. By combining these two functions into a single circuit block, the overall area occupied by the ADC is reduced while maintaining both the reference level generation and dither injection capabilities. The current mirror circuit and random digital signal input integrate these functions without requiring additional dedicated hardware.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250323658A1Pipeline analog-to-digital converter

Publication Date: 2025.10.16 CHONGQING GIGACHIP TECH CO LTD

AI summary

A pipeline analog-to-digital converter includes N pipeline conversion stages cascaded in sequence, and in the first N−1 pipeline conversion stages, at least one pipeline conversion stage includes a dither generating module and a multiplying digital-to-analog conversion module. In the present application, a flash-type analog-to-digital conversion unit in the multiplying digital-to-analog conversion module includes a quantization reference level generating circuit, and under the action of a random digital signal, the quantization reference level of a comparator in the flash-type analog-to-digital conversion unit is shifted by the quantization reference level generating circuit, thereby equivalently adding a dither signal to an input analog signal.