Pipeline ADC DAC Element Swapping for Linearity Improvement
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Solution Overview
Problem
Analog-to-digital converters (ADCs), particularly continuous time pipeline converters, face challenges in maintaining linearity due to mismatch in digital-to-analog converter (DAC) unit elements, leading to harmonic distortion and quantization error leakage, which degrades conversion quality.
Innovation Solution
The technique involves swapping unit element values between different converter stages within an ADC device, using a control device to randomly select and swap unit element values across DACs, effectively linearizing the converters and minimizing gain errors by making the average gain error of all DACs equal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DAC unit elements are matched accurately during fabrication, then linearity performance is improved, but manufacturing precision requirements increase and cost increases
Solution Approach 1:
The patent applies dynamic element matching (DEM) where the mapping between digital input codes and DAC unit elements is changed dynamically over time. A randomization sequence is generated and applied to permute the unit element assignments, transforming static mismatch errors into time-varying noise that can be filtered, thereby resolving the contradiction between manufacturing precision and linearity performance
Solution Approach 2:
The patent changes the parameter of unit element assignment from fixed to time-varying. By applying a randomization sequence that permutes the mapping between digital codes and unit elements over time, the systematic errors caused by fabrication mismatches are converted into random noise, improving linearity without requiring higher manufacturing precision
2Reliability
If dynamic element matching is applied to linearize DAC, then linearity is improved, but noise floor in signal band increases
Solution Approach 1:
The patent employs periodic dithering sequences applied to the digital input codes before DAC conversion. These periodic sequences modulate the quantization errors and mismatch errors to higher frequency bands, allowing the noise to be pushed out of the signal band where it would otherwise increase the noise floor, thus maintaining linearity while controlling noise
Solution Approach 2:
The patent applies preliminary processing to the digital codes through dithering and randomization before they reach the DAC. By pre-modulating the codes with known sequences and applying element matching in advance, the system prepares the signal in a way that minimizes the impact of DAC imperfections, reducing the noise floor while maintaining linearity
3Object-affected harmful factors
If data weighted averaging is used to shift error power to higher frequencies, then in-band noise floor is reduced, but device complexity increases
Solution Approach 1:
The patent segments the DAC unit elements into multiple groups and applies different weighting factors to each group based on the dithering sequence. This segmentation allows the error power to be distributed and shifted to higher frequencies through controlled modulation, reducing in-band noise while managing complexity through systematic grouping rather than individual element control
4Measurement precision
If linear gain error is minimized in DACs, then conversion accuracy is improved, but quantization error leakage increases in pipeline converters
Solution Approach 1:
The patent applies feedback through the randomization and dithering processes where the digital codes are modulated based on previously applied sequences. This feedback mechanism ensures that quantization errors and gain errors are decorrelated from the input signal, preventing systematic leakage while maintaining high conversion accuracy through the statistical properties of the randomized mapping
Data Source
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AI summary
There is described an analog-to-digital converter, ADC, device (100), comprising: i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13); ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to: swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).