Pipeline ADC Error Correction Circuit for Low-Latency Linearity
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Solution Overview
Problem
Pipeline analog-to-digital converters face limitations in performance and speed due to errors in digital-to-analog converters (DAC) and amplifiers, which result in degradation of linearity and signal-to-noise ratio (SNR), particularly at high speeds.
Innovation Solution
Embedding Dynamic Element Matching (DEM) and Harmonic Distortion Correction (HDC) functions within the circuitry of a coarse ADC and rearranging digital calibration blocks to accurately estimate and correct DAC and amplifier errors, minimizing propagation time and increasing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Dynamic Element Matching (DEM) and Harmonic Distortion Correction (HDC) functions are implemented as separate blocks in the pipeline ADC, then DAC and amplifier errors can be corrected, but the propagation delay increases and latency is excessive for high-speed operation
Solution Approach 1:
The patent combines the DEM and HDC functions into a single integrated circuit block within the pipeline ADC stage. The DEM circuit permutes DAC elements to randomize mismatch errors, while the HDC circuit simultaneously corrects harmonic distortion from the residue amplifier. By merging these previously separate functions into one unified block, the patent reduces the number of discrete signal paths and minimizes propagation delay, enabling high-speed operation at 250 MSPS and above while maintaining accurate error correction.
2Measurement precision
If DEM permutation is applied to correct DAC element mismatches, then linearity improves, but additional processing delay is introduced in the critical signal path
Solution Approach 1:
The DEM circuit performs preliminary permutation of DAC elements before the signal proceeds through the rest of the pipeline stage. By pre-randomizing the DAC element mismatches through permutation, the circuit ensures that subsequent signal processing operates on already-corrected data, minimizing the need for additional correction steps and reducing overall propagation delay while maintaining linearity.
3Measurement precision
If multiple random sequences are added to estimate and cancel DAC noise, then signal-to-noise ratio improves, but device complexity and processing delay increase
Solution Approach 1:
The integrated circuit block performs multiple functions simultaneously: it generates random sequences for DAC noise estimation, implements DEM permutation for linearity correction, and executes HDC for harmonic distortion cancellation. By making this single circuit block universal and multi-functional, the patent avoids the complexity of implementing these functions through separate dedicated circuits, thereby reducing overall device complexity while maintaining improved signal-to-noise ratio through noise cancellation.
Data Source
AI summary
A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.