Pipeline ADC Differential Front End With Faraday Shielding

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Solution Overview

Problem

Current pipeline analog to digital converter (ADC) circuits face challenges in rejecting common mode noise and reducing ground loops, which affect signal quality and increase component count and power consumption.

Innovation Solution

The implementation of a differential to single-ended (DTS) pipeline ADC with an integrated Faraday shield in the differential sample and hold circuit, which uses switched capacitors and electrostatic shielding to minimize parasitic capacitances and reduce noise, allowing for efficient signal sampling and conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a traditional pipeline ADC circuit is used, then the conversion function is achieved, but common mode noise is not effectively rejected and ground loops increase

Engineering Contradiction:
Improvecommon mode noise rejectionVSAvoidsignal quality
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent divides the ADC circuit into differential stages and single-ended stages alternately arranged in the pipeline. The differential stages reject common mode noise while the single-ended stages process the converted signals, achieving both noise rejection and reliable conversion through functional segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces differential signaling as an intermediary mechanism between the analog input and digital output stages. By converting analog signals to differential form and back, the circuit creates an intermediate representation that inherently rejects common mode noise while maintaining signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If traditional pipeline ADC circuitry is used, then conversion is achieved, but the number of components and power consumption increase

Engineering Contradiction:
Improvecomponent countVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent merges the differential to single-ended conversion function directly into the pipeline ADC stages by alternating differential and single-ended stages. This integration eliminates the need for separate conversion circuits, reducing component count while maintaining the power efficiency benefits of differential signaling.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each stage in the pipeline is designed to perform multiple functions: differential stages simultaneously achieve noise rejection and signal conditioning, while single-ended stages handle conversion and preparation for the next differential stage. This multi-functionality reduces the overall component count and power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively rejects common mode noise, reduces ground loops, decreases the number of components required, and lowers power consumption while maintaining signal quality and dynamic range.

Implementation Method 1

an integrated Faraday shield in the differential sample and hold circuit, which uses switched capacitors and electrostatic shielding to minimize parasitic capacitances and reduce noise

Methodology Applied
Scientific EffectElectrostatic shielding: Faraday Cage

Data Source

PatentUS12107594B2Differential to single ended pipeline analog to digital converter
Publication Date: 2024.10.01 DUNMORE CIRCUITS LLC
  • US12107594B2 patent drawing
  • US12107594B2 patent drawing
  • US12107594B2 patent drawing

AI summary

A pipeline analog to digital converter includes a “k” number of stages and an output data register. A first stage of the “k” number of stages is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output. A second stage of the “k” number of stages is configured to receive the first single ended analog output and produce a second digital output. The output data register is configured to generate an output digital value based on the first and second digital outputs.