Pipeline ADC Control Circuit for Reduced MDAC Gate Delay
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Solution Overview
Problem
Pipeline ADCs face increased power consumption due to gate delays caused by latch circuits between the multiplying digital-to-analog converter (MDAC) and sub-ADC, limiting the MDAC's ability to utilize the amplification phase effectively.
Innovation Solution
A control circuit is introduced between the sub-ADC and MDAC, utilizing switches and buffer circuits to manage reference voltages and control signals, allowing the MDAC to directly receive reference voltages without the need for intermediate signal processing, thereby reducing gate delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a latch circuit is placed between the sub-ADC and MDAC to store the output value, then the output value can be temporarily stored, but gate delays occur that prevent the MDAC from using the amplification phase completely, resulting in increased power consumption area
Solution Approach 1:
The latch circuit is configured to hold the output value ready for the MDAC before the amplification phase begins, ensuring the data is prepared in advance. This preliminary action allows the MDAC to immediately use the stored value when the amplification phase starts, minimizing idle time and reducing the required operational amplifier size and power consumption area.
Solution Approach 2:
The latch circuit acts as an intermediary between the sub-ADC and MDAC, buffering the output value and managing the timing interface. This intermediary component decouples the timing requirements of the two circuits, allowing the MDAC to operate efficiently without being constrained by gate delays from the sub-ADC side.
2Reliability
If a latch circuit is placed between the sub-ADC and MDAC to store the output value, then the output value can be temporarily stored, but gate delays occur that reduce the operational speed of the pipeline ADC
Solution Approach 1:
The latch circuit holds the output value ready in advance before the MDAC needs it, performing the storage action preliminarily. This ensures that when the amplification phase begins, the data is already prepared and available, minimizing the actual delay experienced during the critical amplification operation and maintaining higher operational speed.
Solution Approach 2:
The latch circuit serves as a timing intermediary that decouples the speed differences between the sub-ADC output and MDAC input requirements. By buffering the data with controlled timing, it prevents gate delays from propagating through the critical signal path, thereby preserving the overall operational speed of the pipeline ADC.
Data Source
AI summary
A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.