Double-Sampled Pipeline ADC Midpoint Latching Timing
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Solution Overview
Problem
Conventional pipelined ADCs face limitations in conversion efficiency due to the sacrifice of hold time for strobe time, requiring very fast comparators to achieve high efficiency, which leads to potential noise issues and differential nonlinearity errors.
Innovation Solution
The proposed double-sampled pipeline ADC system latches intrastage digital quantization signals approximately midway between the leading and trailing edges of clock signals, allowing for extended time to resolve disturbances and reducing the need for extremely fast comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If end sampling comparison is used with leading edge clock triggering, then data throughput is increased by double sampling, but hold time is sacrificed for strobe time thereby limiting conversion efficiency
Solution Approach 1:
The patent applies dynamic timing by using two different clock edges (leading edge for sampling, trailing edge for comparison) to create flexible timing windows. This allows the system to adapt the hold time and strobe time dynamically within each clock cycle, optimizing both throughput and conversion efficiency simultaneously
Solution Approach 2:
The patent implements periodic double sampling by utilizing both the leading and trailing edges of alternating clock cycles. This periodic use of both clock edges enables the system to achieve double data throughput while maintaining adequate hold time through proper phase alignment of the sampling and comparison operations
2Loss of time
If hold time is extended to improve conversion efficiency, then noise susceptibility and differential nonlinearity errors increase
Solution Approach 1:
The patent applies preliminary action by performing the comparison operation during the hold period rather than at its end. By triggering the comparison on the trailing edge of the clock cycle (after sampling is complete but during hold time), the system allows the signal to settle completely before comparison begins, eliminating noise susceptibility and differential nonlinearity errors while maintaining adequate hold time
3Loss of time
If very fast comparators are used to reduce strobe time, then conversion efficiency improves, but device complexity and potential noise issues increase
Solution Approach 1:
The patent applies dynamic timing by utilizing the trailing edge of the clock cycle for comparison operations. This dynamic approach effectively extends the available comparison time without requiring faster comparators, as the comparison occurs during the hold period when the signal is already stable, thereby reducing strobe time requirements while maintaining conversion efficiency with standard comparator speeds
Data Source
AI summary
A double-sampled pipeline analog-to-digital conversion (ADC) system and method in which latching of the intrastage digital quantization signals occurs approximately midway the leading and trailing edges of the clock signals.