Pipeline ADC Comparator Offset Randomization for Missing Codes

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Solution Overview

Problem

Pipeline analog-to-digital converters (ADCs) in image sensors suffer from pronounced missing codes due to capacitor mismatch, limited operational-amplifier gain, and inaccurate reference voltages, leading to degraded image quality, which existing calibration circuits attempt to mitigate but at the cost of increased power consumption and space.

Innovation Solution

Applying a randomized offset to the comparator input in the sub-ADC of the pipeline ADC to redistribute errors, making missing codes less visible or imperceptible in the digital output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If calibration circuits are included in the pipeline ADC to reduce missing codes and improve image quality, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvemissing code reductionVSAvoidcalibration circuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the calibration circuit from the pipeline ADC system. Instead of including calibration circuits to reduce missing codes, the invention accepts the presence of missing codes and uses a different approach (image processing techniques) to achieve the desired image quality, thereby eliminating the complex calibration circuitry.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary processing stage between the ADC output and the final image display. Rather than trying to perfect the ADC output through calibration circuits, the invention uses image processing algorithms as an intermediary to correct or mask the effects of missing codes, achieving the desired result without modifying the ADC hardware.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If calibration circuits are included in the pipeline ADC to reduce missing codes, then manufacturing precision is improved, but power consumption increases

Engineering Contradiction:
Improvemissing code reductionVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent removes the power-consuming calibration circuits from the system by extracting this function and replacing it with post-processing techniques that consume less power, thereby maintaining image quality while reducing overall power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using hardware calibration circuits to correct missing codes, the patent creates a software/digital copy of the correction process through image processing algorithms, which can achieve similar results with lower power consumption.

Inventive Principle:
Principle #26Copying

3Manufacturing precision

If calibration circuits are included in the pipeline ADC to reduce missing codes, then manufacturing precision is improved, but area occupied on die increases

Engineering Contradiction:
Improvemissing code reductionVSAvoiddie area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the calibration circuit blocks from the die, eliminating the need for additional area allocation. The missing code correction function is transferred to post-processing stages that do not require physical space on the image sensor die.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8648913B2Missing code redistribution in pipeline analog to digital converter
Publication Date: 2014.02.11 OMNIVISION TECHNOLOGIES INC
  • US8648913B2 patent drawing
  • US8648913B2 patent drawing
  • US8648913B2 patent drawing

AI summary

A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC). The sub-ADC includes a comparator and a random offset controller. The comparator is coupled to compare a first analog signal received by the stage with a reference signal. The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC.