Pipeline ADC Capacitor Partitioning for Amplifier Offset Cancellation

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Solution Overview

Problem

Pipeline ADCs face accuracy issues due to amplifier offset voltage accumulation, which affects the input-output transfer curve and is critical in applications requiring absolute conversion accuracy.

Innovation Solution

The solution involves partitioning capacitors in a specific ratio to form smaller and larger capacitors, where the smaller capacitors are used for offset compensation, allowing the amplifier's offset to be effectively canceled out, thereby maintaining the same capacitive load and noise properties as the standard 1.5 bits-per-stage architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If amplifier sharing between adjacent stages is used to reduce power consumption, then power consumption is reduced, but amplifier offset voltage accumulates and affects conversion accuracy

Engineering Contradiction:
Improvepower consumptionVSAvoidconversion accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The feedback capacitor C1 is segmented into two separate capacitors: a main feedback capacitor (C1b) and a compensation capacitor (C1a). This segmentation allows the compensation capacitor to specifically target and cancel the amplifier offset voltage while the main feedback capacitor maintains the primary feedback function, thereby resolving the accuracy degradation caused by amplifier sharing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compensation capacitor C1a acts as an intermediary element that mediates between the amplifier offset voltage and the feedback signal. By introducing this intermediate compensation path, the offset voltage can be canceled independently without affecting the main feedback loop, thus maintaining conversion accuracy while enabling amplifier sharing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If standard 1.5 bits-per-stage architecture is used, then conversion accuracy is maintained, but power consumption increases due to dedicated amplifiers per stage

Engineering Contradiction:
Improveconversion accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The feedback capacitor structure is designed with multi-functionality: the main feedback capacitor C1b provides the primary feedback function for signal conversion, while the compensation capacitor C1a provides offset cancellation. This universal capacitor design enables a single amplifier to serve multiple stages while maintaining both accuracy and enabling power reduction through amplifier sharing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If amplifier offset is not compensated, then device complexity is reduced, but input-output transfer curve accuracy deteriorates

Engineering Contradiction:
Improvecircuit complexityVSAvoidtransfer curve accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The offset compensation function is merged with the existing feedback capacitor structure rather than being implemented as a separate compensation circuit. By combining the compensation capacitor C1a with the main feedback capacitor C1b in parallel, the patent achieves offset compensation without adding significant circuit complexity, thus resolving the trade-off between complexity and accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20140111361A1Apparatus, method and system for cancelling an input-referred offset in a pipeline ADC
Publication Date: 2014.04.24 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20140111361A1 patent drawing
  • US20140111361A1 patent drawing
  • US20140111361A1 patent drawing

AI summary

An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter.