Pipeline ADC Offset Compensation Using a Capacitor-Array DAC

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Solution Overview

Problem

Pipeline-type analog-to-digital converters face increased circuit complexity due to the need for offset voltage compensation, which affects conversion accuracy and speed.

Innovation Solution

Incorporating a capacitor array in the digital-to-analog converter circuit to supply an offset compensation voltage, reducing the circuit scale and enhancing conversion precision by compensating for offset voltages in the analog signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a circuit and control system for compensating offset voltage are provided additionally, then conversion accuracy is improved, but circuit complexity increases

Engineering Contradiction:
Improveconversion accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the offset compensation function with the existing D-A converter circuit by integrating an offset compensation capacitor into the capacitor array. This allows the D-A converter to perform both its primary function of converting digital signals to analog and the secondary function of providing offset compensation voltage, thereby improving conversion accuracy without adding separate compensation circuits or control systems.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The D-A converter circuit is designed to serve multiple functions: it converts digital output signals to analog signals for residual signal generation, and simultaneously provides offset compensation voltage to the sample-and-hold circuit. This multi-functionality eliminates the need for dedicated offset compensation hardware, reducing overall circuit complexity while maintaining high conversion accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If multiple conversion processings are implemented, then conversion accuracy is improved, but conversion speed decreases

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent implements preliminary offset compensation by providing the offset compensation voltage from the D-A converter to the sample-and-hold circuit before the analog-to-digital conversion process begins. This preliminary action removes offset voltage errors in advance, allowing subsequent conversion stages to operate with higher accuracy without requiring additional processing time, thus maintaining conversion speed while improving accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The D-A converter acts as an intermediary element that bridges the digital output stage and the analog input stage. It converts digital signals back to analog form to generate residual signals and simultaneously provides offset compensation voltage, enabling multiple conversion processings to occur efficiently without significant speed penalty by mediating between different signal domains.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7764214B2Analog-to-digital converter for converting input analog signal into digital signal through multiple conversion processings
Publication Date: 2010.07.27 SEMICON COMPONENTS IND LLC
  • US7764214B2 patent drawing
  • US7764214B2 patent drawing
  • US7764214B2 patent drawing

AI summary

A sub-A-D converter circuit converts a sampled analog signal into a digital signal of a predetermined number of bits. a D-A converter circuit converts the digital signal converted by the sub-A-D converter circuit into an analog signal to generate a residual signal to be processed by a subsequent conversion processing where the analog signal is to be removed from an analog signal to be sampled by the sub-A-D converter circuit. The D-A converter circuit is of a capacitor array type, and an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor in the capacitor array.