Pipeline ADC Residue-Based Offset Correction for Sub-ADC Errors
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Solution Overview
Problem
Pipeline Analog to Digital Converters (ADCs) face offset errors due to timing and voltage mismatches between sub-ADC stages, leading to inaccuracies in digital code representation of input signals.
Innovation Solution
An offset correction block is introduced to adjust parameters such as the sampling clock phase or threshold voltages to minimize deviations in residue signals, ensuring they fall within an expected range, thereby correcting timing and voltage offset errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional correction circuits or components are added to pipeline ADC stages to correct offset errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by using the existing residue signal from each ADC stage to automatically detect and correct its own offset errors. The correction mechanism utilizes the natural operation outputs (residue signals) of the ADC stages themselves, requiring no external correction inputs or additional sensing components. The system corrects its own errors using internally generated signals, thereby improving measurement precision without adding device complexity.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the threshold voltage parameter of the flash ADC based on detected offset errors. Instead of adding complex hardware, the system modifies the operating parameter (threshold voltage) of existing components to compensate for timing and voltage offsets. This parameter adjustment approach enables error correction while maintaining the simplicity of the original ADC stage architecture.
2Measurement precision
If additional correction circuits are implemented in pipeline ADC stages, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback by continuously monitoring the residue signal range at the output of each ADC stage and using this information to adjust the threshold voltage parameter. The system establishes a feedback loop where the residue signal characteristics are detected, compared against expected ranges, and used to generate correction signals that adjust the threshold voltage. This feedback mechanism improves measurement precision by ensuring residue signals remain within expected ranges, while the simplicity of the feedback path avoids increasing device complexity.
Solution Approach 2:
The patent applies universality by designing the offset correction mechanism to handle multiple types of errors (timing offsets and voltage thresholds) using a single integrated approach. The same correction circuitry and parameter adjustment mechanism work for both timing-related and voltage-related offset errors, making the correction system multi-functional. This universal approach improves measurement precision across different error types without requiring separate correction circuits for each error source, thereby avoiding increased device complexity.
3Reliability
If offset correction mechanisms are added to ADC stages, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by using the existing residue signal from each ADC stage to automatically detect and correct its own offset errors. The correction mechanism utilizes the natural operation outputs (residue signals) of the ADC stages themselves, requiring no external correction inputs or additional sensing components. The system corrects its own errors using internally generated signals, thereby improving reliability without adding device complexity.
4Measurement precision
If parameter adjustments are made to correct timing offsets, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements self-service by automatically detecting timing offsets through residue signal analysis and self-correcting by adjusting the threshold voltage parameter without external intervention. The system uses its own operating signals to identify and correct timing synchronization issues, eliminating the need for manual timing calibration or complex external control mechanisms. This automatic self-correction improves measurement precision while maintaining ease of operation.
Solution Approach 2:
The patent implements feedback by continuously monitoring residue signals for timing offset indicators and automatically adjusting parameters in response. The feedback loop detects timing synchronization errors through residue signal characteristics and triggers automatic parameter adjustments to correct the timing offsets. This closed-loop feedback mechanism improves measurement precision while eliminating manual intervention, thereby maintaining ease of operation.
Data Source
AI summary
An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).