Pipeline ADC Encoding Circuit for Digital Comparator Offset Correction
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Solution Overview
Problem
Conventional pipeline ADCs face issues with comparator offset voltage correction, leading to increased circuit complexity, layout routing challenges, and reduced accuracy due to analog domain corrections and the introduction of non-ideal jitter and noise.
Innovation Solution
A digital correction method is employed using a comparator circuit with parallel comparators, a first encoding circuit for pairwise NAND operations, an encoding control circuit with a random number generator for probability-based selection, and a second encoding circuit with switching transistors to correct comparator offset voltages, eliminating the need for analog domain interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog domain correction is used to correct comparator offset voltage, then correction effectiveness is improved, but circuit complexity and layout routing difficulty increase
Solution Approach 1:
The patent replaces the analog domain correction mechanism with a digital domain correction mechanism. Instead of using analog circuits to correct comparator offset voltages, the invention uses digital logic circuits (NAND gates, flip-flops, multiplexers) to detect and correct offset errors. This substitution simplifies the circuit structure and makes layout routing easier while maintaining correction effectiveness.
2Measurement precision
If analog domain correction is used to correct comparator offset voltage, then correction effectiveness is improved, but noise and jitter increase due to non-ideal analog behavior
Solution Approach 1:
The patent substitutes analog correction circuits with digital correction circuits. The digital logic operations (NAND operations on comparator outputs, digital multiplexing based on control signals) are immune to noise and jitter that plague analog circuits. This eliminates the harmful analog effects while preserving the offset correction functionality.
3Speed
If multiple comparators are enabled by the same clock and operate simultaneously, then conversion speed is improved, but encoding circuit complexity increases
Solution Approach 1:
The patent segments the encoding function into modular units. Each comparator output pair is processed by dedicated NAND gate logic, and the results are accumulated systematically. This segmentation allows parallel processing of multiple comparator outputs without requiring a monolithic complex encoder, thus maintaining high conversion speed while managing encoding circuit complexity through modular design.
Data Source
AI summary
A device for encoding pipeline ADC includes: a comparator circuit connected to differential input signals and outputting a plurality of comparison results; a first encoding circuit, performing a pairwise NAND operation on the plurality of comparison results to output a plurality of NAND operation results, and outputting a first signal or/and a second signal based on the plurality of NAND operation results and the level of a first selection signal under the control of a clock signal; an encoding control circuit, generating a second selection signal based on the occurrence probability of each signal in a first digital code, receiving a third signal and a fourth signal and outputting a first selection signal according to the level of the second selection signal; a second encoding circuit, outputting a second digital code according to the first digital code under the control of switching of a plurality of switching transistors.