Pipeline ADC Redundant Comparator Layout for Offset Tolerance
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Solution Overview
Problem
Pipeline type analog-digital converters face challenges due to comparator offset tolerance issues, which affect yield factor and accuracy, especially with reduced circuit area and power consumption, making it difficult to maintain required yield and reliability.
Innovation Solution
Implementing a redundant configuration for comparators in the pipeline type analog-digital converter, where an auxiliary comparator can replace a comparator with an offset exceeding tolerance, improving yield factor and accuracy by alleviating offset margin constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the circuit area and power consumption are reduced by decreasing element size, then power consumption and area are improved, but the comparator offset tolerance deteriorates, making it difficult to maintain required yield and reliability
Solution Approach 1:
The patent applies preliminary action by performing offset error detection before final product operation. A test mode is implemented that detects comparator offset errors in advance, allowing defective comparators to be identified and compensated for before the converter enters normal operation, thus ensuring high yield without requiring larger comparators
Solution Approach 2:
The patent changes the operational parameters of the comparator by implementing dual-mode operation. In test mode, the comparator operates with enhanced detection capabilities to measure offset errors. In normal mode, the comparator operates with standard parameters. This parameter switching allows small comparators to be fully characterized and compensated, resolving the contradiction between small size and reliability
2Area of moving object
If the circuit area is reduced by decreasing element size, then area is improved, but the comparator offset tolerance deteriorates, affecting accuracy and yield
Solution Approach 1:
The patent detects offset errors in advance during a test mode before normal operation. This preliminary detection allows the system to identify and compensate for manufacturing variations in small comparators, ensuring that area reduction does not compromise manufacturing precision
Solution Approach 2:
The patent implements feedback by using the detected offset error information to adjust the operation of the comparator. The measured offset is fed back into the system to compensate for the error, allowing small comparators with tighter tolerances to achieve the required manufacturing precision through active correction
3Area of stationary object
If the element size is reduced to improve power consumption and area, then power and area are improved, but the offset error detection capability deteriorates, affecting reliability
Solution Approach 1:
The patent performs offset error detection in a dedicated test mode before normal operation. This preliminary measurement action allows the system to characterize the offset of small elements without requiring larger dimensions during the actual measurement process, maintaining detection capability despite reduced element size
Data Source
AI summary
A pipeline type analog-digital converter includes a first to an N-th (N is an integer of not less than 2) stages (101 to 10N) brought into cascade connection and converting an analog signal input from a preceding stage to a digital signal of a predetermined bit and outputting the digital signal. Each of the first to the (N−1)-th stages (101 to 10N−1) includes an analog-digital converter circuit including comparators comparing an analog signal with reference potential being determined in advance and mutually different in parallel. The first to the (N−1)-th stages are in redundant configuration with the comparators of the stage including an auxiliary comparator.