Pipeline ADC Single-Bit Redundancy Correction for Overflow Detection
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Solution Overview
Problem
High-speed and high-resolution pipeline A/D converters face challenges with increased layout area, power consumption, and input/output delay due to excessive pipeline stages, as well as the inability to identify negative and positive overflows of input signals in existing digital correction methods.
Innovation Solution
The proposed solution involves a pipeline A/D converter with a reduced number of stages, utilizing a single redundancy bit digital correction method where each substage quantizes the input voltage to generate a quantized thermometer code, subtracts the corresponding analog voltage, amplifies and shifts the residual voltage, and introduces negative and positive redundancy codes to identify overflows, reducing the number of pipeline stages and amplifier count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the conventional 1.5-bit/stage pipeline structure is used, then high resolution A/D conversion is achieved, but the number of pipeline stages increases greatly, increasing layout area and power consumption
Solution Approach 1:
The patent divides the A/D conversion process into multiple pipeline stages, where each stage performs partial conversion and passes intermediate results to the next stage. This segmentation allows the system to achieve high resolution through cumulative processing across stages rather than requiring all comparators in a single stage, thereby reducing the area required per stage while maintaining overall resolution.
Solution Approach 2:
The patent introduces a time dimension to the conversion process by using pipelined architecture, where conversions proceed through multiple stages over time rather than completing in a single parallel stage. This allows resolution to be accumulated across stages sequentially, reducing the spatial area required at any given moment while achieving the same overall resolution.
2Measurement precision
If the conventional 1.5-bit/stage pipeline structure is used, then high resolution A/D conversion is achieved, but the number of pipeline stages increases, increasing power consumption
Solution Approach 1:
The conversion process is segmented into multiple stages, each handling a portion of the total conversion workload. This distributes power consumption across stages rather than concentrating it in a single large parallel structure, allowing for more efficient energy utilization while achieving high resolution through cumulative processing.
Solution Approach 2:
The pipelined architecture implements periodic action by cycling through stages in sequence, where each stage processes data at optimized intervals. This periodic processing allows components to be in active states only when needed, reducing overall power consumption compared to having all components continuously active in a single large parallel stage.
3Measurement precision
If the number of pipeline stages is increased, then A/D conversion resolution is improved, but input/output delay time increases
Solution Approach 1:
The conversion process is divided into segments that can be processed in parallel across multiple stages, with each stage handling a specific portion of the conversion. This segmentation allows overlapping processing of different data through the pipeline, reducing the overall time required compared to sequential processing, while still achieving high resolution through cumulative stage results.
4Measurement precision
If the full reference voltage range is used by each substage, then quantization range is maximized, but no spare reference voltage range remains for introducing negative and positive redundancy bit codes
Solution Approach 1:
Each pipeline stage performs partial conversion rather than complete conversion, processing only a portion of the total conversion requirement. This partial action leaves room in the reference voltage range for redundancy codes, while the cumulative effect of multiple stages achieves the full quantization range needed for high resolution conversion.
Solution Approach 2:
The patent introduces intermediary redundancy bit codes that act as mediators between the quantization process and overflow detection. These intermediary codes occupy the spare reference voltage range and enable overflow identification without interfering with the primary quantization function, thus maintaining both quantization range and adaptability.
Data Source
AI summary
A pipeline A/D converter and its single redundancy bit digital correction are provided. The single redundancy bit digital correction includes the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; the code and offset code of each substage corresponding to the quantized thermometer code are calculated; the offset codes of all stages are added by weight to get total offset code; and codes of all substages are added by weight, to which the total offset code is added. The comparator offset error is corrected to obtain an output code which identifies the negative or positive overflow of input signals. The A/D converter adopting the above digital correction is provided.