Pipeline ADC Error Correction Using PRBS Correlation
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Solution Overview
Problem
Analog-to-digital converters (ADCs) introduce errors during signal conversion, leading to inaccurate digital representations, particularly due to gain and memory errors in high-speed pipeline ADCs, which current error correction methods are slow to address.
Innovation Solution
An error correcting ADC system comprising multiple segments and a digital backend with error estimation and correction circuits that use pseudo-random binary sequences to rapidly determine and correct gain and memory errors by correlating current and delayed residue signals, reducing the number of digital samples and convergence time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional error correction methods are used in high-speed pipeline ADCs, then gain and memory errors can be corrected, but the convergence time is slow and requires many digital samples
Solution Approach 1:
The patent applies preliminary action by pre-generating pseudo-random binary sequences (PRBS) and storing them in memory before the error correction process begins. These pre-prepared sequences are then used during the correction process to accelerate convergence, eliminating the need to generate random sequences during the time-critical correction phase.
Solution Approach 2:
The patent replaces traditional mechanical/random sequence generation methods with a deterministic pseudo-random binary sequence approach. By using predetermined PRBS stored in memory and correlating them with residue signals, the system achieves faster error correction convergence without relying on slow random number generation processes.
2Measurement precision
If traditional error correction methods are used in high-speed pipeline ADCs, then gain and memory errors can be corrected, but a large number of digital samples are required
Solution Approach 1:
The patent substitutes traditional random sampling methods with a deterministic pseudo-random binary sequence correlation approach. By using pre-generated PRBS stored in memory and correlating them with residue signals through digital signal processing, the system achieves accurate error correction with significantly fewer digital samples required.
Solution Approach 2:
The patent performs preliminary preparation by storing pseudo-random binary sequences in memory before the correction process. This pre-computation allows the system to use these sequences efficiently during error correction, reducing the total number of samples needed compared to methods that generate random sequences on-the-fly during correction.
3Speed
If multiple ADC segments are used to improve conversion speed, then high-speed conversion is achieved, but gain errors and memory errors are introduced
Solution Approach 1:
The patent implements feedback by using the output residue signals from ADC segments and correlating them with pre-stored pseudo-random binary sequences to detect gain and memory errors. The detected errors are then fed back to correct the digital output, creating a closed-loop system that maintains both high speed and high accuracy.
Solution Approach 2:
The patent divides the ADC into multiple segments that operate in parallel to achieve high-speed conversion. Each segment processes a portion of the conversion task, and the patent's error correction method specifically addresses the gain and memory errors introduced by this segmentation through PRBS correlation and digital signal processing.
Data Source
AI summary
A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.