Pipeline ADC First Stage With Switched-Capacitor Programmable Gain
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Solution Overview
Problem
Existing pipeline ADC designs face challenges in implementing a programmable gain function without using an additional programmable gain amplifier (PGA), especially in low-speed designs where the sample-and-hold amplifier (SHA) may not be utilized, making it difficult to provide programmable gain.
Innovation Solution
Incorporating a programmable gain function into the first pipeline stage using switched capacitor (SC) circuits, where the sub-ADC and MDAC provide different gains by controlling switches, allowing the selection of gains such as x1 and x4, eliminating the need for an additional PGA stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an additional programmable gain amplifier (PGA) stage is added to provide programmable gain function, then the ADC achieves programmable gain capability, but the device complexity and circuit structure are increased
Solution Approach 1:
The patent merges the programmable gain function with the existing first pipeline stage by integrating gain control into the sub-ADC and MDAC circuits. The switched capacitor circuits in these existing components are controlled to provide different gain values (x1 or x4) without adding a separate PGA stage, thus achieving functionality merging that reduces overall device complexity.
Solution Approach 2:
The sub-ADC and MDAC circuits in the first pipeline stage are designed to perform multiple functions: they serve as both the quantization and multiplication functions of a standard pipeline stage, and simultaneously provide programmable gain amplification. By making these existing circuits multi-functional through switch control, the patent eliminates the need for dedicated PGA hardware.
2Device complexity
If the SHA is not used in low-speed pipeline ADC designs, then the device complexity is reduced, but the ability to implement programmable gain function is lost
Solution Approach 1:
The patent extracts the programmable gain function from the SHA module and relocates it to the first pipeline stage. This allows the SHA to be omitted in low-speed designs while the gain function remains available through the sub-ADC and MDAC circuits, which can operate independently to provide both quantization and programmable gain amplification.
Solution Approach 2:
The first pipeline stage's sub-ADC and MDAC circuits are designed to self-provide the programmable gain function that would traditionally require the SHA. By making these circuits self-sufficient in providing gain amplification, the system can eliminate the SHA in low-speed applications without losing programmable gain capability.
3Adaptability or versatility
If an additional PGA stage is added to provide programmable gain, then the gain function is achieved, but the productivity and processing speed are reduced
Solution Approach 1:
The patent combines the gain amplification function with the quantization and multiplication operations in the first pipeline stage. By merging these functions into a single stage rather than adding a separate PGA stage, the signal processing pipeline maintains its original speed characteristics without the additional processing delay that would result from an extra amplification stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the provision of programmable gain without an additional PGA stage, enhancing the flexibility and efficiency of the ADC design, particularly in low-speed applications where the SHA is optional or not used.
Implementation Method 1
The sub-ADC and MDAC are implemented by switched capacitor (SC) circuits. In the sub-ADC and MDAC, different capacitances are provided to provide different gains by controlling switches in the SC circuits.
Data Source
AI summary
A pipeline analog-to-digital converter (ADC) comprises a plurality of pipeline stages is disclosed. The first pipeline stage has programmable gain function. The first pipeline stage includes a sub-analog-to-digital converter (sub-ADC) and a multiplying digital-to-analog converter (MDAC) implemented by switched capacitor (SC) circuits. Different capacitances in the sub-ADC and MDAC are provided so as to provide different gains by controlling switches in the SC circuits.