Pipeline ADC Calibration for Incomplete Quantization at High Clock Speed
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Solution Overview
Problem
Pipeline analog-to-digital converters face inaccuracies due to comparator circuits failing to generate correct quantization results within the shortened cycle time as clock speed increases, leading to incorrect digital output codes.
Innovation Solution
A pipeline analog-to-digital converter system with multiple converter circuitries and a calibration circuitry that detects quantization completion and adjusts digital codes by combining first digital codes, using valid signals and delay signals to determine whether to set the output code to one of several predetermined codes, ensuring accurate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speed is increased to improve conversion speed, then productivity is improved, but comparator circuits cannot generate correct quantization results within the shortened cycle time, leading to manufacturing precision degradation
Solution Approach 1:
The patent applies dynamics by making the operation period of each conversion stage adjustable rather than fixed. The controller dynamically configures the number of operation periods for each stage based on signal characteristics, allowing the system to adapt the conversion time to ensure accurate quantization results even at high clock speeds. This resolves the contradiction by enabling fast conversion when possible while maintaining accuracy when needed.
Solution Approach 2:
The patent changes the parameter of operation period duration for each conversion stage. By allowing different stages to have different numbers of operation periods (e.g., first stage has 1 period, second stage has 2 periods, third stage has 3 periods), the system can optimize the balance between conversion speed and quantization accuracy. This parameter adjustment enables the comparator circuits to complete accurate quantization within the available time at high clock speeds.
2Device complexity
If fixed operation period is used for each conversion stage, then device complexity is reduced, but conversion accuracy deteriorates when clock speed increases
Solution Approach 1:
The patent introduces dynamic control of operation periods through a controller that configures each conversion stage based on signal characteristics. This dynamic approach maintains relatively simple circuit structures while achieving high accuracy by adaptively adjusting the number of operation periods. The controller manages the complexity, allowing fixed-stage architectures to achieve variable precision without requiring complex variable-structure circuits.
3Ease of operation
If uniform conversion time is allocated to all stages, then ease of operation is improved, but conversion precision is reduced for signals requiring different quantization times
Solution Approach 1:
The patent implements dynamic allocation of operation periods to different conversion stages based on signal characteristics. The controller automatically determines the appropriate number of operation periods for each stage, providing ease of operation through automatic adaptation while achieving high precision for various signal types. This eliminates the need for manual configuration while ensuring each stage receives appropriate time allocation.
Solution Approach 2:
The patent performs preliminary configuration of operation periods based on signal characteristics before the actual conversion process. The controller analyzes the input signal and pre-determines the optimal number of operation periods for each stage, ensuring that the conversion process can proceed with high accuracy without requiring real-time adjustments during conversion. This preliminary action maintains ease of operation while achieving precision.
Data Source
AI summary
A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.