Pipeline ADC Front-End Sampling Without Sample-and-Hold Delay

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Solution Overview

Problem

Conventional ADC stage designs require front-end sample-and-hold circuits, which introduce noise, strain operational capabilities, and limit the frequency range of analog input signals due to the need for precisely matched sampling networks in flash comparators and residual generators.

Innovation Solution

A pipeline ADC front-end sampling structure that provides a continuous time input signal to the flash comparator, eliminating the need for a sample-and-hold circuit by pre-charging input capacitors and applying the analog input signal directly, allowing for faster propagation and higher bandwidth processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a front-end sample-and-hold circuit is used to ensure proper operation of the ADC stage, then the flash comparator and residual generator can operate on the same sample, but noise is introduced and power requirements increase

Engineering Contradiction:
Improveproper operation of ADC stageVSAvoidnoise introduction
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes the front-end sample-and-hold circuit from the ADC stage, extracting the harmful noise-generating component while preserving the essential function through alternative means. The residual generator's sampling network directly samples the continuous-time input signal, eliminating the need for a separate S/H circuit and its associated noise and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The sampling network of the residual generator is designed to serve dual purposes: it samples the continuous-time input signal for the residual generation function, and simultaneously provides the sampled signal to the flash comparator. This multi-functional approach eliminates the need for dedicated sampling hardware while ensuring both components operate on the same sample.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a front-end sample-and-hold circuit is used to ensure proper operation of the ADC stage, then the flash comparator and residual generator can operate on the same sample, but power requirements increase

Engineering Contradiction:
Improveproper operation of ADC stageVSAvoidpower requirements
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the front-end sample-and-hold circuit from the ADC stage, extracting the harmful noise-generating component while preserving the essential function through alternative means. The residual generator's sampling network directly samples the continuous-time input signal, eliminating the need for a separate S/H circuit and its associated noise and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The sampling network of the residual generator is designed to serve dual purposes: it samples the continuous-time input signal for the residual generation function, and simultaneously provides the sampled signal to the flash comparator. This multi-functional approach eliminates the need for dedicated sampling hardware while ensuring both components operate on the same sample.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If sampling networks of the residual generator and flash comparator are precisely matched, then both can operate on the same sample, but the frequency range of analog input signals is limited

Engineering Contradiction:
Improvesame sample operationVSAvoidfrequency range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent removes the front-end sample-and-hold circuit from the ADC stage, extracting the harmful noise-generating component while preserving the essential function through alternative means. The residual generator's sampling network directly samples the continuous-time input signal, eliminating the need for a separate S/H circuit and its associated noise and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using a front-end S/H circuit to sample the input signal and then distributing it to both the residual generator and flash comparator, the patent inverts the approach by having the residual generator's sampling network directly sample the continuous-time input signal and provide it to both components. This reversal eliminates the bandwidth limitations of traditional S/H circuits.

Inventive Principle:
Principle #13The other way round (Inversion)

4Reliability

If a front-end sample-and-hold circuit is used, then proper operation is ensured, but the operational capabilities of the residual generator are strained

Engineering Contradiction:
Improveproper operation of ADC stageVSAvoidoperational capabilities strain
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the front-end sample-and-hold circuit from the ADC stage, extracting the harmful noise-generating component while preserving the essential function through alternative means. The residual generator's sampling network directly samples the continuous-time input signal, eliminating the need for a separate S/H circuit and its associated noise and power consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The sampling network of the residual generator is designed to serve dual purposes: it samples the continuous-time input signal for the residual generation function, and simultaneously provides the sampled signal to the flash comparator. This multi-functional approach eliminates the need for dedicated sampling hardware while ensuring both components operate on the same sample.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7652611B2Front-end sampling technique for analog-to-digital converters
Publication Date: 2010.01.26 ANALOG DEVICES INC
  • US7652611B2 patent drawing
  • US7652611B2 patent drawing
  • US7652611B2 patent drawing

AI summary

Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.