Pipeline ADC Clocking Without Front-End SHA to Minimize Sampling Mismatch

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Solution Overview

Problem

Pipeline Analog-to-Digital Converters (ADCs) without a front-end Sample-and-Hold Amplifier (SHA) suffer from significant sampling mismatch, leading to performance deterioration due to the absence of a front-end SHA, which is power-consuming and occupies a large area, and introduces noise and non-linear characteristics affecting the entire ADC.

Innovation Solution

The method involves dividing the Q2 clock into QS and QL phases, allowing the MDAC and flash ADC to simultaneously sample the analog input signal during the QS phase, and the preamp to amplify and convert it during the QL phase, thereby minimizing sampling mismatch without additional power consumption or area increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a front-end SHA is included in the pipeline ADC, then sampling mismatch between MDAC and flash ADC is minimized, but power consumption increases and chip area increases

Engineering Contradiction:

Improvesampling mismatchVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The invention removes the front-end SHA from the pipeline ADC structure, extracting the problematic component that caused high power consumption and large chip area. The sampling function is then distributed to the MDAC and flash ADC themselves, which perform simultaneous sampling without requiring a dedicated front-end SHA circuit.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The MDAC and flash ADC serve their own sampling needs by simultaneously sampling the input signal directly, without relying on an external front-end SHA. Each component performs its sampling function independently at the same time point, making the system self-sufficient and eliminating the need for the power-consuming SHA circuit.

Inventive Principle:

Principle #25Self-service

2Measurement precision

If a front-end SHA is included in the pipeline ADC, then sampling mismatch between MDAC and flash ADC is minimized, but chip area increases

Engineering Contradiction:

Improvesampling mismatchVSAvoidchip area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The sampling function previously performed by the separate front-end SHA is merged into the simultaneous operation of the MDAC and flash ADC. Both components sample the input signal at the same time point through coordinated clocking, combining the sampling function into the existing conversion circuitry rather than requiring a separate dedicated circuit.

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by moving object

If a pipeline ADC without front-end SHA is used, then power consumption is reduced and chip area is reduced, but sampling mismatch occurs leading to performance deterioration

Engineering Contradiction:

Improvepower consumptionVSAvoidperformance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The invention uses periodic clock signals with specific phase relationships to coordinate the simultaneous sampling operation of the MDAC and flash ADC. The clock phases ensure that both components sample at the same time point periodically, maintaining consistent timing alignment across conversion cycles and preventing sampling mismatch.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The invention implements timing feedback mechanisms where the clock signal phases are designed to account for and compensate for any timing differences between the MDAC and flash ADC sampling paths. This feedback-based timing coordination ensures that both components sample at the correct time point, maintaining performance reliability without requiring a front-end SHA.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7583219B2Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same

Publication Date: 2009.09.01 ELECTRONICS & TELECOMM RES INST

AI summary

Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.