Pipeline ADC Stage Capacitor Segmentation for Faster Low-Power Conversion
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Solution Overview
Problem
Conventional pipeline A/D converting circuits face issues with scaling capacitance values between stages sharing an operational amplifier, leading to reduced speed and increased power consumption, and amplify error voltage inefficiently.
Innovation Solution
The pipeline A/D converting circuit divides the sampling capacitor of one stage into multiple capacitors, using some as sampling capacitors for the next stage, reducing capacitance and allowing for error voltage cancellation during operational amplification, thereby reducing power consumption and improving response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sampling capacitor of one stage is divided into multiple capacitors and some are used as sampling capacitors for the next stage, then the capacitive load of subsequent stages is reduced and response speed is improved, but the circuit complexity increases
Solution Approach 1:
The sampling capacitor of one stage is divided into multiple capacitors (e.g., Cf11, Cf12, Cs11, Cs12). Some of these divided capacitors are then used as sampling capacitors for the next stage, reducing the capacitive load and improving response speed while managing complexity through structured segmentation.
2Use of energy by moving object
If capacitance values are scaled between stages sharing an operational amplifier, then power consumption is reduced, but speed decreases
Solution Approach 1:
Different capacitors have different capacitance values optimized for their specific functions. The feedback capacitors (Cf) and sampling capacitors (Cs) have different values, allowing each to be optimized locally for its role while sharing the operational amplifier, thus reducing overall power consumption without sacrificing speed.
3Device complexity
If the amplifier is shared by multiple stages, then device count is reduced, but error voltage amplification efficiency decreases
Solution Approach 1:
The operational amplifier uses feedback capacitors (Cf) to stabilize the amplification process. By sharing the amplifier with proper feedback mechanisms and timing control, the circuit maintains error voltage amplification efficiency while reducing the total number of devices through resource sharing.
4Use of energy by moving object
If sampling capacitors are interleave-controlled and used across stages, then power consumption is reduced and response speed is improved, but control complexity increases
Solution Approach 1:
The sampling capacitors are interleave-controlled with periodic timing signals (phi1, phi2, phi3, phi4). This periodic control allows the same capacitors to be used in different stages at different times, reducing power consumption and improving speed while managing control complexity through regular timing patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the capacitive load of subsequent stages, allowing for faster response and lower power consumption while effectively canceling computation errors, outperforming traditional methods in terms of speed and efficiency.
Implementation Method 1
an amplifier, for which the sampling capacitor that has sampled the input signal voltage is connected as a feedback capacitor in an operational amplification time period, in which the amplifier amplifies a difference voltage between the sampled voltage of the input signal and reference voltage
Implementation Method 2
a sampling capacitor that samples input signal voltage from a preceding stage
Implementation Method 3
a sub digital-to-analog converter for selecting a reference voltage that corresponds to the digital signal from the sub analog-to-digital converter
Data Source
AI summary
Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.