Pipeline ADC Two-Stage Comparison to Cut Comparator Count
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Solution Overview
Problem
Conventional pipeline analog-to-digital converters (ADCs) have a high number of comparators, leading to increased area occupation and power consumption, which worsens with higher precision levels.
Innovation Solution
The proposed ADC design reduces the number of comparators by using a two-stage comparison process, where a first comparison circuit performs a coarse comparison and a second comparison circuit performs a fine comparison, using a minimal number of comparators to achieve accurate digital quantification, thereby reducing the overall area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pipeline ADC structure with multiple comparators is used, then measurement precision is improved, but device area and power consumption increase
Solution Approach 1:
The patent divides the comparison process into two separate stages: a first comparison circuit performs coarse comparison to determine the most significant bit, and a second comparison circuit performs fine comparison to determine the least significant bit. This segmentation allows each comparator to be simpler and fewer in number, reducing total area while maintaining precision
Solution Approach 2:
The first comparison circuit performs preliminary coarse comparison before the second comparison circuit performs fine comparison. By establishing the coarse result first, the system can then focus resources on refining just the necessary precision level rather than using multiple full-precision comparators simultaneously
2Measurement precision
If conventional pipeline ADC structure with multiple comparators is used, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the comparison function into two separate circuits with different precision levels, the patent reduces the total number of comparators needed. Fewer comparators directly translate to lower dynamic power consumption while the two-stage process maintains the required measurement precision
Solution Approach 2:
The patent changes the precision parameter of comparators across different stages - the first comparison circuit uses lower precision for coarse comparison, while the second uses higher precision for fine comparison. This parameter variation optimizes the balance between power consumption and measurement accuracy
3Measurement precision
If higher precision level is implemented in conventional pipeline ADC, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the high-precision comparison task into two separate lower-precision comparison circuits. Instead of using one complex high-precision comparator, the system uses a first comparison circuit for coarse comparison and a second comparison circuit for fine comparison, reducing overall device complexity
Data Source
AI summary
An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity.