Pipeline Bubble Removal via Clock Signal Blocking
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Solution Overview
Problem
Existing methods for removing pipeline bubbles in ASIC designs require significant changes to the pipeline architecture, leading to increased area and reduced clock rates, compromising performance.
Innovation Solution
A system that detects stalls in the pipeline, replaces invalid data with valid data from adjacent registers, and manipulates clock signals to prevent bubbles from propagating, without altering the pipeline architecture, using a bubble-removal circuit that synthesizes and stitches into the pipeline netlist.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional logic (DMUX) is inserted between pipeline stages to remove bubbles, then bubble removal capability is improved, but device area increases significantly
Solution Approach 1:
The patent extracts the bubble removal function from the data path and implements it through clock signal control. Instead of adding DMUX logic to manipulate data, the invention removes bubbles by selectively blocking clock signals to downstream registers, thereby preventing propagation of invalid data without adding data path complexity.
Solution Approach 2:
The patent introduces clock signal control as an intermediary mechanism between pipeline stages. The bubble removal logic acts as a mediator that monitors data validity and controls clock signal propagation accordingly, enabling bubble removal without direct modification of the data path architecture.
2Productivity
If additional logic (DMUX) is inserted between pipeline stages to remove bubbles, then bubble removal capability is improved, but maximum clock rate decreases
Solution Approach 1:
The patent extracts the bubble removal function from the data path and implements it through clock signal control. Instead of adding DMUX logic to manipulate data, the invention removes bubbles by selectively blocking clock signals to downstream registers, thereby preventing propagation of invalid data without adding data path complexity.
Solution Approach 2:
The patent uses periodic clock signal control to manage bubble propagation. By enabling or disabling clock signals at specific periods based on data validity detection, the system achieves bubble removal while maintaining the original pipeline timing and maximum clock rate capability.
3Device complexity
If pipeline bubbles are allowed to propagate, then architecture remains simple, but data latency increases
Solution Approach 1:
The patent detects pipeline stalls and identifies bubbles in advance before they can propagate through the entire pipeline. By detecting when downstream memory is full and identifying registers containing invalid data, the system takes preliminary action to block clock signals and prevent bubble propagation, thereby reducing latency without complex architectural changes.
Solution Approach 2:
The patent implements feedback mechanisms where bubble removal logic continuously monitors the pipeline state, detects invalid data in registers, and dynamically controls clock signal propagation. This feedback-driven approach enables the system to adaptively remove bubbles as they are detected, reducing latency while maintaining simple architecture.
4Device complexity
If pipeline bubbles are allowed to propagate, then no additional control logic is needed, but power consumption increases
Solution Approach 1:
The patent detects pipeline stalls and identifies bubbles in advance before they can propagate through the entire pipeline. By detecting when downstream memory is full and identifying registers containing invalid data, the system takes preliminary action to block clock signals and prevent bubble propagation, thereby reducing latency without complex architectural changes.
Solution Approach 2:
The bubble removal logic serves itself by automatically detecting bubbles and controlling clock signals without requiring external intervention. The system monitors its own pipeline state and autonomously blocks clock signals to prevent bubble propagation, achieving power savings through self-managed bubble removal.
Data Source
AI summary
One embodiment of the present invention provides a system that removes a bubble from a pipeline. During operation, the system first detects a stall in the pipeline. The system next determines whether a first register contains invalid data, which is associated with a bubble. Next, the system determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the system replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register. As a result, the system removes the invalid data from the pipeline.