Multi-Stage Pipeline Calculation Circuit for AI Data Processing
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Solution Overview
Problem
Existing calculation chips, especially in the artificial intelligence field, face limitations in flexibility, performance, execution speed, execution efficiency, and power consumption due to their hardware architecture, which leads to increased on-chip I/O data throughput and calculation overheads.
Innovation Solution
A hardware architecture that supports multi-stage pipeline calculation using groups of pipeline calculation circuits, where each group constitutes a multi-stage calculation pipeline with stages of calculation circuits arranged to perform corresponding instructions, allowing for parallel pipeline operations and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional instruction sets are used in calculation chips, then the chips can complete general control operations and data processing, but the hardware architecture limits flexibility and increases on-chip I/O data throughput requirements
Solution Approach 1:
The patent segments the calculation instruction into multiple micro-instructions that can be executed in parallel by different pipeline stages. Each micro-instruction handles a specific operation (e.g., data loading, computation, storage), allowing the system to process multiple operations simultaneously and reduce I/O throughput requirements while improving flexibility.
Solution Approach 2:
The patent introduces a multi-dimensional pipeline architecture with multiple parallel execution paths. By adding temporal dimension through pipelining and spatial dimension through parallel pipelines, the system achieves higher flexibility without proportionally increasing I/O throughput, as operations are distributed across multiple dimensions.
2Productivity
If multiple operations are implemented using traditional instructions, then the calculation chip can perform complex tasks, but the number of instructions increases substantially leading to increased I/O data throughput
Solution Approach 1:
The patent merges multiple traditional instructions into a single compound instruction that is decomposed into micro-instructions for parallel execution. This merging reduces the total number of instruction cycles required and decreases I/O throughput demands while maintaining or improving execution efficiency for complex operations.
Solution Approach 2:
The patent implements continuous pipeline execution where each stage performs its operation continuously without waiting for other stages to complete. This continuous action maintains high productivity while reducing the peak I/O throughput requirements compared to sequential instruction execution.
3Speed
If traditional calculation instructions are used, then the calculation chip can perform operations, but the execution speed and power consumption have room for improvement
Solution Approach 1:
The patent implements dynamic pipeline configuration where the system can adaptively enable or disable pipeline stages based on the specific operation being executed. This dynamic approach allows the chip to achieve high execution speed for suitable operations while consuming less power by activating only the necessary pipeline stages, rather than maintaining all stages in a fixed configuration.
Data Source
AI summary
A calculation apparatus is included in a combined processing apparatus, which also includes a general interconnection interface and other processing apparatuses. The calculation apparatus interacts with other processing apparatuses to jointly complete calculations specified by users. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to a device and other processing apparatuses and is used for storing data of the device and data of other processing apparatuses. Operational efficiency of calculation of every kind of data processing fields including an artificial intelligence field can be improved, thereby decreasing overall overheads and cost of the calculation.