Pipeline CDAC with Shared Capacitor for Low-Power Accurate Conversion
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Solution Overview
Problem
Conventional cyclic digital to analog converters (CDACs) face issues with large power consumption and size due to increased operation frequency, and they still suffer from charge injection errors, which affect accuracy and efficiency.
Innovation Solution
A cyclic digital to analog converter in a pipeline structure where two CDAC blocks share a charging capacitor, reducing size and power consumption while compensating for charge injection errors through strategic switching and parasitic component management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operation frequency is increased to improve conversion speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The CDAC is divided into multiple pipeline stages (first CDAC block, second CDAC block, etc.), where each stage processes a portion of the conversion task. This segmentation allows parallel processing of different digital signals simultaneously, improving overall conversion speed without requiring a single high-frequency operation that would consume excessive power.
Solution Approach 2:
The charging capacitor is shared across multiple CDAC blocks, serving as a common resource for charging operations in each stage. This multi-functional use of the capacitor reduces the total number of capacitors needed, thereby reducing overall circuit size and power consumption while maintaining the ability to serve multiple processing stages.
2Productivity
If more CDAC blocks are added to pipeline structure to improve conversion speed, then productivity is improved, but device complexity increases
Solution Approach 1:
Multiple CDAC blocks share common components including the charging capacitor, amplifier, and control logic. By merging these resources across pipeline stages, the patent reduces the total component count and interconnections needed, thereby lowering device complexity while maintaining the parallel processing capability for improved conversion speed.
Solution Approach 2:
The amplifier and charging capacitor serve multiple CDAC blocks simultaneously, performing the same function across different pipeline stages. This universal usage reduces the number of duplicate components needed, simplifying the overall circuit architecture while enabling faster conversion through parallel operation.
3Volume of moving object
If CDAC size is reduced to meet smaller display requirements, then weight and volume are improved, but charge injection errors increase affecting accuracy
Solution Approach 1:
The patent extracts and compensates for parasitic capacitances (such as switch parasitic capacitance) that cause charge injection errors. By identifying and separately managing these parasitic elements through compensation techniques, the system can use smaller capacitor values without sacrificing accuracy, thereby reducing overall CDAC size while maintaining conversion precision.
Solution Approach 2:
The patent employs compensation techniques that adjust operational parameters and switching sequences to counteract charge injection effects. By changing the control strategy and timing parameters rather than simply increasing component sizes, the system achieves accurate conversion with smaller physical dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and prevents charge injection errors, achieving efficient digital-to-analog conversion with improved accuracy and smaller size, aligning with the trend towards smaller LCDs.
Implementation Method 1
a charging capacitor for charging according to the digital signal input
Implementation Method 2
a first storing capacitor for storing the first analog value
Implementation Method 3
The amplifier differentially amplifies and outputs the uniform reference voltage VCOM and the voltage stored in the second node N2
Data Source
AI summary
A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.