Pipeline Circuit Architecture for In-Memory Computation
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Solution Overview
Problem
In-memory computation for pattern recognition in machine learning applications consumes significant energy due to regular memory accesses, which is inefficient in terms of power and time.
Innovation Solution
A pipelined, multi-stage architecture that performs in-memory computations within a memory device, allowing for localized data processing and reducing the need for external memory access, with each stage comprising a memory array and associated circuitry that can perform computations and store results back to the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If regular memory accesses are used for pattern recognition computations, then computation functionality is achieved, but energy consumption increases significantly
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated structure. Memory cells store data while associated circuitry performs computations directly on the stored data, eliminating the need for separate memory access operations and reducing energy consumption by combining these two functions in one location.
Solution Approach 2:
The patent introduces an intermediary pipeline architecture between the processor and memory system. This pipeline includes multiple stages with memory arrays and associated circuitry that perform in-memory computations, acting as an intermediate processing layer that reduces the burden on both the processor and traditional memory system.
2Loss of time
If regular memory accesses are performed for computations, then data processing is achieved, but processing time increases
Solution Approach 1:
The patent segments the computation process into multiple pipeline stages, each with its own memory array and associated circuitry. This segmentation allows different stages to process different data simultaneously, enabling parallel processing and reducing overall processing time through the pipeline architecture.
Solution Approach 2:
The patent performs preliminary computations within the memory device itself before data needs to be transferred to the processor. By performing computations in advance within the memory system, the patent reduces the amount of data that needs to be transferred and processed externally, thereby reducing processing time.
3Use of energy by moving object
If in-memory computation is implemented, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic configuration capabilities within the memory device, allowing the associated circuitry to be configured for different computation operations. This dynamic reconfigurability enables the same hardware structure to perform multiple computation functions, reducing the need for dedicated circuitry for each operation and managing complexity through flexibility.
Data Source
AI summary
Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.