Packet Processing Pipeline Circuit Virtualized Rate Limiting
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Solution Overview
Problem
Existing network appliances struggle to efficiently manage network traffic by effectively rate limiting network packet production, leading to potential packet drops and resource overconsumption.
Innovation Solution
A system that includes a first packet processing pipeline circuit producing network packets and a second packet processing pipeline circuit with match-action processing stages implementing limiters and a rate limit calculator, which together determine and enforce rate limiting decisions to govern network packet production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If network packets are processed without effective rate limiting, then packet processing speed is improved, but packet drops and resource overconsumption occur
Solution Approach 1:
The rate limiting function is segmented into multiple independent limiters (first limiter, second limiter, third limiter) that operate in parallel within the packet processing pipeline. Each limiter independently monitors and controls different aspects of packet generation, allowing high-speed processing while preventing resource overconsumption through distributed control.
Solution Approach 2:
The system implements feedback mechanisms where limiters generate limiting indicators that feed back to the packet processing pipeline. The rate limit calculator processes these indicators and adjusts packet transmission rates dynamically, ensuring reliable resource allocation while maintaining high processing speed through continuous monitoring and adjustment.
2Reliability
If rate limiting is implemented to prevent resource overconsumption, then resource allocation fairness is improved, but packet processing complexity increases
Solution Approach 1:
Multiple rate limiting functions are merged into a unified packet processing pipeline structure. The first, second, and third limiters are integrated within the same processing stage, sharing common resources and control logic. This merging reduces overall system complexity while maintaining fair resource allocation through coordinated operation of the limiters.
Solution Approach 2:
The packet processing pipeline is designed with multi-functionality, where the same pipeline structure handles both packet processing and rate limiting operations. The limiters and rate limit calculator are implemented within the existing pipeline framework, allowing a single system to perform multiple functions without proportionally increasing complexity.
3Measurement precision
If multiple limiters are used to enforce rate limiting decisions, then rate limiting accuracy is improved, but processing time increases
Solution Approach 1:
The limiters perform preliminary actions by pre-calculating and pre-positioning limiting indicators before the main packet processing completes. The rate limit calculator processes these pre-generated indicators in advance, enabling accurate rate limiting decisions to be made without adding significant processing time to the main packet transmission path.
Data Source
AI summary
The rate limiter circuits in the packet processing chip of a NIC are a limited hardware resource that may limit the number of workloads that can be run on a server. Some such chips include an egress packet processing pipeline circuit and a second packet processing pipeline circuit that prepares work for the egress pipeline circuit. Some of the stages of the second pipeline circuit can be configured as a first limiter and a second limiter that implement aspects of different rate limiters such as IOPS limiters, bandwidth limiters, etc. Another pipeline stage can use the outputs of the different rate limiters to make a limiting decision that is written into one of the rate limiter circuits. The second pipeline circuit is thereby implementing virtualized rate limiters where one of the rate limiter circuits performs the rate limiting for the virtualized rate limiters.