Pipeline Clock Driving Circuit with Independent Pulse Width Delay
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Solution Overview
Problem
The existing pipeline clock driving circuits in cryptocurrency chip architectures face challenges in optimizing the pulse clock width and delay between operation stages, leading to lower operating frequencies and worse system performance due to the dependency of pulse clock width on the delay between stages.
Innovation Solution
The proposed pipeline clock driving circuit includes a trigger, a delay module with first and second delay sub-modules, and a combinational logic module, allowing for independent control of pulse clock width and delay between stages, enabling finer adjustments to improve computing efficiency and system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the pulse clock width is determined by the delay module delay time, then the clock timing is simplified, but the operating frequency is limited due to the dependency on delay between stages
Solution Approach 1:
The delay module is segmented into two independent sub-modules: a first delay sub-module that determines pulse clock width, and a second delay sub-module that determines delay between stages. This segmentation allows independent optimization of pulse width and stage delay, enabling higher operating frequencies without increasing overall timing complexity.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the delay times of the first and second delay sub-modules can be independently adjusted. This dynamic adjustability allows the system to optimize performance for different operating conditions, achieving higher operating frequencies while maintaining manageable clock timing complexity.
2Device complexity
If a single delay module is used to generate delayed clock signals for next stage, then the circuit structure is simplified, but the pulse clock width cannot be independently optimized
Solution Approach 1:
The single delay module is divided into two specialized sub-modules: the first delay sub-module dedicated to generating pulse clocks with optimized width, and the second delay sub-module dedicated to providing delayed clock signals to the next stage. This segmentation maintains relatively simple circuit structure while enabling independent optimization of pulse clock width.
Solution Approach 2:
Each delay sub-module is optimized for its specific function: the first delay sub-module is configured to provide appropriate pulse width for reliable latch operation, while the second delay sub-module is configured to provide the optimal delay for pipeline stage synchronization. This local optimization enables versatile pulse clock width adjustment without significantly increasing overall circuit complexity.
3Productivity
If the delay between pulse clocks of adjacent stages is reduced, then the pipeline throughput is improved, but the pulse clock width becomes insufficient for reliable latch operation
Solution Approach 1:
By segmenting the delay function into two independent sub-modules, the patent enables the first delay sub-module to maintain adequate pulse clock width while the second delay sub-module minimizes the delay between stages. This segmentation resolves the contradiction by allowing the pulse width and inter-stage delay to be independently optimized, achieving high pipeline throughput without compromising latch operation reliability.
Data Source
AI summary
The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage clock driving circuit.