Pipeline Clock Driving Circuit for Stable Pulse Width Across Stages
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Solution Overview
Problem
The existing pipeline clock driving circuits in mining machine type chips for generating cryptocurrency face issues with duty cycle deviations due to manufacturing errors in combinational logic devices, leading to inadequate pulse width in later stages, which fails to meet the minimum pulse width requirements for operation stages.
Innovation Solution
A pipeline clock driving circuit design where each stage generates a pulse clock signal with a pulse width independent of its input signal, using a trigger, delay module, and combinational logic module to ensure consistent pulse width across stages, with the delay module composed of inverters and optionally data selectors to adjust pulse width and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is transferred stage by stage through the pipeline clock driving circuit, then the working clock is provided to each operation stage, but manufacturing errors in combinational logic devices cause duty cycle deviations that result in inadequate pulse width in later stages
Solution Approach 1:
The clock driving circuit is divided into multiple independent stages, where each stage generates its own pulse clock signal independently. This segmentation prevents the accumulation of duty cycle deviations that would occur in a cascaded structure, as each stage's pulse width is determined by its own delay module rather than being affected by previous stage errors
Solution Approach 2:
Each stage employs a delay module that feeds back the delayed clock signal to the combinational logic module. This feedback mechanism ensures that the pulse width is precisely controlled by the delay time, compensating for any manufacturing variations in the logic devices and maintaining consistent pulse widths across all stages
2Stability of the object's composition
If the pulse clock width is determined by the delay time of the delay module, then consistent pulse width can be achieved, but manufacturing errors in combinational logic devices still cause duty cycle deviations
Solution Approach 1:
Each stage is designed with its own delay module and combinational logic module, creating locally independent pulse generation units. This local quality approach ensures that each stage maintains its own pulse width characteristics without being affected by manufacturing errors in other stages, achieving both consistency and error isolation
Data Source
AI summary
This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.