Pipeline Control Circuit for Memory Bank Data Collision Management
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in data transfer between DRAM and CPU cores due to differences in address input methods for read and write operations, leading to degraded data rates and increased latency.
Innovation Solution
A semiconductor device with a pipeline control circuit and delay buffer that manages data transfer on a common read/write bus, allowing independent read/write operations across multiple memory cores with pipelined access cycles, and using a multiplexer and demultiplexer to synchronize data transfer with a shorter read/write clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common read/write bus is used for multiple memory banks, then device complexity is reduced, but data collisions occur between simultaneous read and write operations
Solution Approach 1:
The pipeline control circuit predicts whether a data collision will occur by examining the command sequence in advance. When a collision is predicted between read and write operations on the same bank, the circuit proactively controls the delay buffer to hold the read data until the write operation completes, preventing the collision before it occurs.
Solution Approach 2:
The delay buffer serves as an intermediary element between the read data path and the write data path on the common bus. It temporarily stores read data when needed, allowing the pipeline control circuit to mediate between simultaneous read and write operations and prevent data collisions without requiring separate dedicated buses.
2Speed
If read data is immediately output to the bus, then data transmission speed is improved, but data collisions occur with subsequent write operations
Solution Approach 1:
The pipeline control circuit performs preliminary prediction of data collisions by analyzing the command sequence. When a collision is predicted, it proactively controls the delay buffer to hold the read data before the write operation occurs, preventing the collision while maintaining optimal throughput by only delaying when necessary.
Solution Approach 2:
The pipeline control circuit continuously monitors the command sequence and provides feedback control to the delay buffer. Based on the predicted collision status, it dynamically adjusts whether to hold or output read data, creating a closed-loop control system that optimizes both speed and reliability.
3Reliability
If separate buses are used for read and write operations, then data collision is prevented, but device complexity and resource usage increase
Solution Approach 1:
The invention merges the read and write data paths into a single common bus, reducing device complexity and resource usage. The pipeline control circuit with delay buffer provides the necessary collision prevention, allowing the system to achieve the reliability of separate buses with the simplicity of a combined bus structure.
Solution Approach 2:
The delay buffer acts as an intermediary that enables a single common bus to function reliably for both read and write operations. It temporarily holds read data when write operations are pending, allowing the common bus to be shared without data collisions, thus achieving the benefits of merging while maintaining reliability.
4Productivity
If pipeline operation is implemented across multiple banks, then productivity is improved, but coordination complexity between banks increases
Solution Approach 1:
The pipeline control circuit is designed with a universal prediction mechanism that handles multiple memory banks through a unified command sequence analysis approach. The same delay control logic applies to each bank, allowing scalable pipeline operation across any number of banks without proportionally increasing control complexity.
Solution Approach 2:
The system segments the memory system into multiple independent banks that can operate in parallel pipeline stages. Each bank is controlled by the same type of pipeline control circuit, allowing independent optimization of each segment while maintaining overall system productivity through coordinated pipeline operation.
Data Source
AI summary
A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.