Pipelined Hardware Control Path Verification via Clock Cycle Counting
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Solution Overview
Problem
Verifying the correct operation of pipelined processes in hardware is challenging due to unpredictable events like stalls and interrupts, which complicate data path verification and make exhaustive simulation-based solutions infeasible.
Innovation Solution
A method and system that monitor data input and output in a pipelined process, count progressing clock cycles, and evaluate assertions to ensure data is output at the expected time, simplifying control path verification by focusing on progressing clock cycles and ignoring non-progressing cycles caused by random events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation-based verification methods are used to verify pipelined hardware designs, then verification coverage can be achieved, but the verification process becomes infeasible due to the complexity and unpredictability of events like stalls and interrupts
Solution Approach 1:
The verification process is segmented into two independent components: data path verification (checking functional correctness of transformations) and control path verification (checking timing and data movement). This segmentation allows control path verification to be performed separately using clock cycle counting, avoiding the need for complex exhaustive simulation of all possible events.
Solution Approach 2:
The control path verification is extracted from the overall verification process. Instead of verifying control logic through exhaustive simulation of all events, the patent extracts only the essential timing information by counting progressing clock cycles, separating this from data path verification and simplifying the overall approach.
2Reliability
If data path verification is performed on pipelined processes, then functional correctness can be verified, but verification is complicated by unpredictable events like stalls and interrupts
Solution Approach 1:
The verification is divided into data path verification (functional correctness) and control path verification (timing). Data path verification can then focus solely on functional transformations without being complicated by control events, as timing verification is handled separately through clock cycle counting.
3Reliability
If exhaustive simulation is used to verify control path, then complete verification coverage can be achieved, but the verification becomes infeasible due to the large number of possible event combinations
Solution Approach 1:
The essential timing verification is extracted from exhaustive simulation. By counting only progressing clock cycles and ignoring non-progressing cycles (stalls, interrupts), the patent achieves control path verification without requiring exhaustive simulation of all possible event combinations, dramatically reducing verification time.
4Measurement precision
If the verification monitors all clock cycles including non-progressing cycles, then complete timing information is captured, but the verification complexity increases due to unpredictable events
Solution Approach 1:
The verification logic applies different treatment to different types of clock cycles. Progressing clock cycles (where data moves through the pipeline) are counted for verification, while non-progressing clock cycles (stalls, interrupts) are ignored. This local differentiation simplifies the verification logic while maintaining accuracy for relevant timing information.
Data Source
AI summary
Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.