Pipeline Error Correction Circuit for PVT-Induced Stage Faults
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Solution Overview
Problem
Existing error detection and correction (EDAC) systems in IoT smart devices face challenges in balancing operation reliability, power consumption, and implementation cost, particularly due to errors caused by PVT variations, which current pipeline processing architectures fail to adequately address.
Innovation Solution
The proposed solution involves a pipeline stage circuit with a master latch circuit, error detection circuit, multiplexer, and slave latch circuit for circuit-level error detection and correction, along with a system-level error detection and correction mechanism that activates when continuous errors are detected, stopping operations and flushing data to re-process at a lower frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipeline processing architecture is used to increase operation speed, then productivity is improved, but errors may occur due to PVT variations
Solution Approach 1:
The patent applies preliminary action by detecting errors at the circuit level before they propagate through the pipeline. The error detection circuit compares the input signal with the output signal of each pipeline stage and generates an error state signal, allowing early intervention and correction before errors affect subsequent processing stages.
Solution Approach 2:
The patent implements feedback by using the error state signal to control the multiplexer selection. When an error is detected, the feedback mechanism switches the output to use the original input signal instead of the processed output signal, thereby correcting the error and maintaining reliability while preserving pipeline operation.
2Reliability
If error detection and correction mechanisms are added to pipeline circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection and correction function into modular components that can be integrated into each pipeline stage. The error detection circuit, multiplexer, and control logic are structured as discrete functional blocks that can be independently implemented and combined, reducing overall system complexity.
Solution Approach 2:
The patent implements self-service by enabling each pipeline stage to autonomously detect and correct its own errors through the integrated error detection circuit and multiplexer. The circuit automatically compares signals, generates error state signals, and switches to correct data without requiring external intervention, simplifying the overall control architecture.
3Reliability
If continuous error detection and system-level correction are implemented, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing continuous error detection through clocked operation. The error detection circuit operates periodically with each clock cycle, comparing input and output signals at each pipeline stage. This periodic operation ensures continuous error monitoring while allowing power management through clock gating when the system is idle or in low-power states.
Data Source
AI summary
An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.