Hardware-Software Cooperative Pipeline Error Detection
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Solution Overview
Problem
Compute-class processors face challenges in detecting and correcting pipeline errors, as existing error detection mechanisms like ECC codes leave coverage holes and require additional costly mechanisms like spatial or temporal duplication, which incur high overhead or design complexity.
Innovation Solution
The implementation of SEC-DED-DP and SEC-DP techniques, which involve storing data bits and ECC check bits separately to detect and correct single-bit storage errors without duplicating data or ECC check bits, and using parity bits to distinguish between storage errors and pipeline errors, thereby maintaining error correction capabilities while avoiding mis-correction of pipeline errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial duplication is used to protect against pipeline errors, then reliability is improved, but chip area cost and design complexity increase significantly
Solution Approach 1:
The patent segments the error protection mechanism into separate components: ECC codes are applied only to storage registers, while pipeline stages use lighter-weight detection mechanisms. This segmentation allows each component to be optimized independently, reducing overall chip area while maintaining reliability.
Solution Approach 2:
Different error protection strategies are applied to different parts of the system based on their specific requirements. Storage registers use full ECC protection, while pipeline stages use more area-efficient detection methods. This local quality approach ensures that area-intensive ECC hardware is only deployed where absolutely necessary.
2Reliability
If temporal duplication is used to detect pipeline errors, then reliability is improved, but performance overhead increases significantly
Solution Approach 1:
The patent implements preliminary error detection within the pipeline by placing checkers at strategic points before errors can propagate. This preliminary action allows errors to be detected early in the execution flow, enabling faster recovery and reducing the performance impact compared to post-execution verification methods.
Solution Approach 2:
The design allows the pipeline to continue executing instructions without stopping for error checking, skipping the traditional stop-check-resume cycle. Error detection occurs in parallel with instruction execution, and recovery mechanisms are pre-positioned to minimize disruption to the instruction stream.
3Reliability
If full ECC protection is applied to pipeline operations, then reliability is improved, but hardware cost and design complexity increase
Solution Approach 1:
The patent segments the application of ECC protection to only those pipeline components where it is most beneficial—primarily storage registers and critical data paths. Other pipeline stages use simpler protection mechanisms, reducing overall hardware complexity while maintaining data integrity where it matters most.
Solution Approach 2:
Full ECC protection is applied locally to specific high-risk areas of the pipeline rather than uniformly across all stages. This local quality approach ensures that complex ECC hardware is deployed only where the probability of errors is highest or the impact of errors would be most severe.
4Device complexity
If no error protection is used, then hardware cost is reduced, but coverage holes remain in error detection
Solution Approach 1:
The patent segments error protection into multiple layers: ECC for storage, lighter checkers for pipeline stages, and targeted protection for critical operations. This segmented approach provides comprehensive coverage across all pipeline components without requiring full ECC protection everywhere, balancing cost and reliability.
Solution Approach 2:
The design uses multi-functional error detection mechanisms that can operate in different modes depending on the pipeline stage. A single detection unit can provide both lightweight checking for area efficiency and full ECC-like protection when needed, achieving universal coverage across diverse pipeline components with a unified hardware structure.
Data Source
AI summary
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.