Pipeline Gate Power Gating for Leakage Current Reduction
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Solution Overview
Problem
Integrated circuits face significant power consumption due to leakage current, even when idle, which is not effectively addressed by existing solutions that focus on large architectural features, necessitating additional methods to reduce power usage and heat generation, especially in battery-driven devices.
Innovation Solution
The method involves power-gating logic gates between source and destination storage elements, using control logic to manage power gates based on clock enable signals, allowing current flow during wake states and inhibiting it during sleep states to minimize leakage current, with control logic employing a state machine to ensure timely transition between wake and sleep states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to large architectural features, then power consumption is reduced, but leakage current from small-grained features remains significant
Solution Approach 1:
The patent segments the circuit into pipeline stages with source storage elements, destination storage elements, and intermediate logic gates. Power gating is applied at the gate level within each pipeline stage, allowing fine-grained control of individual gates rather than coarse control of entire functional blocks. This segmentation enables selective power gating of only those gates that are truly idle, reducing leakage current more effectively while avoiding unnecessary complexity.
Solution Approach 2:
The patent applies power gating locally to individual logic gates based on their specific idle status rather than uniformly across entire functional blocks. Each gate's power state is controlled independently based on local signals (source enable, destination enable, and clock signals), allowing precise control of leakage current at the gate level while maintaining overall system performance.
2Speed
If gates are kept awake to maintain performance, then speed is improved, but leakage current increases power consumption
Solution Approach 1:
The patent dynamically controls the power state of each gate based on real-time operational signals. Gates transition between awake and slept states according to the assertion/deassertion of source enable, destination enable, and clock signals. This dynamic control allows gates to be awake only when needed for data transfer, minimizing leakage current while maintaining circuit speed performance.
Solution Approach 2:
The power gating control logic uses locally available signals (source enable, destination enable, clock signals) to automatically control the power state of gates without requiring external control. Each pipeline stage self-regulates its power consumption based on its own operational status, eliminating the need for complex centralized control while reducing leakage current effectively.
3Loss of energy
If power gates are slept to reduce leakage, then power consumption decreases, but current flow is inhibited affecting performance
Solution Approach 1:
The patent ensures that power gates are kept awake in advance before data transfer is needed and are only slept after data transfer is complete. The control logic monitors source enable, destination enable, and clock signals to determine the appropriate timing for transitioning gates between awake and slept states, ensuring current flow reliability when needed while minimizing leakage current when idle.
Solution Approach 2:
The power gating control logic uses feedback from operational signals (source enable, destination enable, clock signals) to continuously adjust the power state of gates. This feedback mechanism ensures that gates remain awake when data transfer is required and transition to slept state when idle, maintaining current flow reliability while reducing leakage current effectively.
Data Source
AI summary
Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.