Pipeline Hazard Detection for Conditional Instructions

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Solution Overview

Problem

Data processing pipelines face inefficiencies due to hazards and stalls caused by dependencies between instructions, particularly when conditional instructions fail their test conditions, leading to unnecessary delays and reduced performance.

Innovation Solution

Incorporating hazard detection circuitry that allows conditional instructions to proceed even if a hazard condition is detected, provided there are no intervening instructions that can update the condition status information, and using duplicated processing resources across pipeline stages to manage operand availability and reduce stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hazard detection circuitry delays processing of a given instruction when a hazard condition is detected, then correctness of instruction processing is maintained, but processing throughput and efficiency deteriorate

Engineering Contradiction:
Improvecorrectness of instruction processingVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the parameter of hazard handling by introducing a conditional flag state that determines whether to enforce or ignore hazard conditions. When the conditional flag indicates a failed test condition and no intervening instructions can update it, the system transitions from enforcing hazard delays to allowing instruction progression, thereby improving throughput while maintaining correctness in cases where the conditional instruction would not execute anyway.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If hazard detection circuitry delays processing of conditional instructions, then data dependencies are resolved, but unnecessary stalls occur when the conditional instruction fails its test condition

Engineering Contradiction:
Improvedata dependency resolutionVSAvoidunnecessary stalls
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary evaluation of the conditional flag state before enforcing hazard delays. By checking whether the conditional instruction's test condition has already failed and whether any intervening instructions can update the condition status, the system determines in advance whether hazard detection should be enforced. This preliminary action prevents unnecessary stalls from occurring in the first place, improving processing efficiency while maintaining data dependency resolution when needed.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If duplicated processing resources are used across pipeline stages, then operand availability is improved, but device complexity increases

Engineering Contradiction:
Improveoperand availabilityVSAvoidpipeline structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements duplicated processing resources that can serve multiple functions across different pipeline stages. These duplicated resources are used to provide operands earlier in the pipeline when needed, improving operand availability and reducing stalls. The duplication is strategically placed at specific stages where it provides maximum benefit for handling hazards and improving throughput, balancing the increased device complexity against the performance gains.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10445101B2Controlling processing of instructions in a processing pipeline
Publication Date: 2019.10.15 ARM LTD
  • US10445101B2 patent drawing
  • US10445101B2 patent drawing
  • US10445101B2 patent drawing

AI summary

In a processing pipeline, hazards involving conditional instructions may be ignored when the conditional instruction would fail its test condition and there are no earlier instructions than the conditional instruction remaining which could potentially update the condition status information used to evaluate the test condition.