Parallel Pipeline Image Processing Apparatus Register Reduction
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Solution Overview
Problem
Existing image processing systems face complexity in controlling pipeline configurations and managing intermediate data registers, particularly in high-density pixel processing for applications like stereo and optical flow processing, leading to increased register requirements and processing complexity.
Innovation Solution
The implementation of a parallel pipeline configuration with multi-stage processing units, including first, second, and third operators, registers, and delay elements, which allows for efficient image processing by managing intermediate data and reducing register capacity through optimized data propagation and delay adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pipeline configuration with multiple stages is used to perform image processing, then processing speed is improved, but the complexity of control and the number of registers required increases
Solution Approach 1:
The image processing is divided into multiple pipeline stages, each handling specific operations (e.g., gradient calculation, correlation computation, matching). This segmentation enables parallel processing across stages, improving throughput while keeping each stage's control logic manageable through clear functional boundaries.
Solution Approach 2:
Delay elements are introduced as intermediary components between pipeline stages to synchronize data flow. These delay elements act as mediators that buffer intermediate results, allowing subsequent stages to process data at the correct timing without requiring complex control logic for data coordination.
2Productivity
If a pipeline configuration with multiple stages is used to perform image processing, then processing speed is improved, but the number of registers required increases
Solution Approach 1:
Multiple pipeline stages share common delay elements and register resources. Instead of dedicating separate registers to each stage, the system merges register usage across stages, allowing the same hardware resources to be reused at different time points in the pipeline, thereby reducing the total number of registers required.
Solution Approach 2:
Delay elements serve as intermediary buffers that reduce the need for extensive register storage. By using delay elements to hold intermediate results temporarily, the system minimizes the number of registers needed while maintaining the pipeline's processing capability.
3Stability of the object's composition
If arithmetic operation results are assigned again as inputs to post-stage arithmetic units, then processing continuity is maintained, but the instruction system becomes complicated
Solution Approach 1:
The pipeline architecture ensures continuous processing by maintaining data flow between stages. Each stage continuously receives input from the previous stage and produces output for the next stage, eliminating idle time and maintaining processing continuity through the pipeline's inherent sequential structure.
Solution Approach 2:
Delay elements act as intermediaries that simplify the instruction system by automatically managing data timing and synchronization between stages. Instead of requiring complex instructions to coordinate data assignment, the delay elements passively ensure that data is available at the correct time, reducing instruction complexity.
Data Source
AI summary
Image processing is made efficient. An image processing apparatus according to an embodiment includes a line memory, a plurality of pipelines, and a line memory control circuit that controls data reading from the line memory to processing units. The processing unit includes a first operator that performs a first arithmetic operation, a second operator which performs a second arithmetic operation based on first intermediate data based on an arithmetic operation result of the first operator and which calculates second intermediate data according to the first intermediate data of when peripheral pixels are sequentially changed, third operators which perform a third arithmetic operation based on the first intermediate data and which calculate third intermediate data according to the first intermediate data of when the peripheral pixels are sequentially changed, and delay elements that delay the third intermediate data.