Processor Pipeline Instruction Combining for Wider Memory Access
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Solution Overview
Problem
Existing processor architectures fail to fully utilize the available bandwidth between the processor and cache or memory due to inefficient execution of load and store instructions that target single 32-bit words, leaving 96 bits unused during execution, despite the interface being 128 bits wide.
Innovation Solution
A method and apparatus for identifying patterns of multiple memory access instructions that reference a common base register and do not fully utilize the available bus width, and replacing them with a single equivalent instruction that utilizes more of the available bus width, such as combining adjacent or non-contiguous memory access instructions into a single cache line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple narrow memory access instructions are executed sequentially, then software compatibility is maintained, but bandwidth utilization is insufficient with 96 bits unused during each instruction execution
Solution Approach 1:
The patent combines multiple narrow memory access instructions (e.g., multiple 32-bit load/store instructions) into a single wide memory access instruction (e.g., 128-bit load/store instruction) that can utilize the full bandwidth of the memory interface. This merging occurs in the instruction pipeline when the processor detects that multiple instructions target adjacent memory locations that can be accessed in a single wide operation, thereby improving bandwidth utilization while maintaining software compatibility through transparent instruction translation
2Measurement precision
If multiple memory access instructions are executed separately, then instruction precision is maintained, but throughput is reduced due to increased instruction count
Solution Approach 1:
The patent merges multiple precise memory access instructions into a single wide instruction that maintains the precision of individual accesses while improving throughput. The processor pipeline detects patterns of multiple instructions accessing adjacent memory locations and combines them into a single wide memory access operation, reducing the total instruction count and increasing throughput without sacrificing the precision of individual memory accesses
Solution Approach 2:
The patent transitions from a scalar dimension (single 32-bit word access per instruction) to a vector dimension (multiple 32-bit words accessed simultaneously in a single 128-bit wide instruction). This dimensional change allows the processor to maintain instruction precision for each individual data element while accessing multiple elements in parallel, thereby increasing throughput without losing precision
3Ease of operation
If the processor pipeline executes narrow instructions, then software compatibility is preserved, but bandwidth utilization remains suboptimal
Solution Approach 1:
The processor pipeline performs self-service by automatically detecting and combining narrow memory access instructions into wide instructions without requiring software modifications. The instruction translation and combination logic is built into the processor hardware, allowing it to self-optimize bandwidth utilization while maintaining compatibility with existing software that was compiled for narrow instruction sets
Data Source
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AI summary
Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.